2 * MCF5227x Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
30 * Interrupt Controller (INTC)
31 *********************************************************************/
32 #define INT0_LO_RSVD0 (0)
33 #define INT0_LO_EPORT1 (1)
34 #define INT0_LO_EPORT4 (4)
35 #define INT0_LO_EPORT7 (7)
36 #define INT0_LO_EDMA_00 (8)
37 #define INT0_LO_EDMA_01 (9)
38 #define INT0_LO_EDMA_02 (10)
39 #define INT0_LO_EDMA_03 (11)
40 #define INT0_LO_EDMA_04 (12)
41 #define INT0_LO_EDMA_05 (13)
42 #define INT0_LO_EDMA_06 (14)
43 #define INT0_LO_EDMA_07 (15)
44 #define INT0_LO_EDMA_08 (16)
45 #define INT0_LO_EDMA_09 (17)
46 #define INT0_LO_EDMA_10 (18)
47 #define INT0_LO_EDMA_11 (19)
48 #define INT0_LO_EDMA_12 (20)
49 #define INT0_LO_EDMA_13 (21)
50 #define INT0_LO_EDMA_14 (22)
51 #define INT0_LO_EDMA_15 (23)
52 #define INT0_LO_EDMA_ERR (24)
53 #define INT0_LO_SCM_CWIC (25)
54 #define INT0_LO_UART0 (26)
55 #define INT0_LO_UART1 (27)
56 #define INT0_LO_UART2 (28)
57 #define INT0_LO_I2C (30)
58 #define INT0_LO_DSPI (31)
59 #define INT0_HI_DTMR0 (32)
60 #define INT0_HI_DTMR1 (33)
61 #define INT0_HI_DTMR2 (34)
62 #define INT0_HI_DTMR3 (35)
63 #define INT0_HI_SCMIR (62)
64 #define INT0_HI_RTC_ISR (63)
66 #define INT1_HI_CAN_BOFFINT (1)
67 #define INT1_HI_CAN_ERRINT (3)
68 #define INT1_HI_CAN_BUF0I (4)
69 #define INT1_HI_CAN_BUF1I (5)
70 #define INT1_HI_CAN_BUF2I (6)
71 #define INT1_HI_CAN_BUF3I (7)
72 #define INT1_HI_CAN_BUF4I (8)
73 #define INT1_HI_CAN_BUF5I (9)
74 #define INT1_HI_CAN_BUF6I (10)
75 #define INT1_HI_CAN_BUF7I (11)
76 #define INT1_HI_CAN_BUF8I (12)
77 #define INT1_HI_CAN_BUF9I (13)
78 #define INT1_HI_CAN_BUF10I (14)
79 #define INT1_HI_CAN_BUF11I (15)
80 #define INT1_HI_CAN_BUF12I (16)
81 #define INT1_HI_CAN_BUF13I (17)
82 #define INT1_HI_CAN_BUF14I (18)
83 #define INT1_HI_CAN_BUF15I (19)
84 #define INT1_HI_PIT0_PIF (43)
85 #define INT1_HI_PIT1_PIF (44)
86 #define INT1_HI_USBOTG_STS (47)
87 #define INT1_HI_SSI_ISR (49)
88 #define INT1_HI_PWM_INT (50)
89 #define INT1_HI_LCDC_ISR (51)
90 #define INT1_HI_CCM_UOCSR (53)
91 #define INT1_HI_DSPI_EOQF (54)
92 #define INT1_HI_DSPI_TFFF (55)
93 #define INT1_HI_DSPI_TCF (56)
94 #define INT1_HI_DSPI_TFUF (57)
95 #define INT1_HI_DSPI_RFDF (58)
96 #define INT1_HI_DSPI_RFOF (59)
97 #define INT1_HI_DSPI_RFOF_TFUF (60)
98 #define INT1_HI_TOUCH_ADC (61)
99 #define INT1_HI_PLL_LOCKS (62)
101 /* Bit definitions and macros for IPRH */
102 #define INTC_IPRH_INT32 (0x00000001)
103 #define INTC_IPRH_INT33 (0x00000002)
104 #define INTC_IPRH_INT34 (0x00000004)
105 #define INTC_IPRH_INT35 (0x00000008)
106 #define INTC_IPRH_INT36 (0x00000010)
107 #define INTC_IPRH_INT37 (0x00000020)
108 #define INTC_IPRH_INT38 (0x00000040)
109 #define INTC_IPRH_INT39 (0x00000080)
110 #define INTC_IPRH_INT40 (0x00000100)
111 #define INTC_IPRH_INT41 (0x00000200)
112 #define INTC_IPRH_INT42 (0x00000400)
113 #define INTC_IPRH_INT43 (0x00000800)
114 #define INTC_IPRH_INT44 (0x00001000)
115 #define INTC_IPRH_INT45 (0x00002000)
116 #define INTC_IPRH_INT46 (0x00004000)
117 #define INTC_IPRH_INT47 (0x00008000)
118 #define INTC_IPRH_INT48 (0x00010000)
119 #define INTC_IPRH_INT49 (0x00020000)
120 #define INTC_IPRH_INT50 (0x00040000)
121 #define INTC_IPRH_INT51 (0x00080000)
122 #define INTC_IPRH_INT52 (0x00100000)
123 #define INTC_IPRH_INT53 (0x00200000)
124 #define INTC_IPRH_INT54 (0x00400000)
125 #define INTC_IPRH_INT55 (0x00800000)
126 #define INTC_IPRH_INT56 (0x01000000)
127 #define INTC_IPRH_INT57 (0x02000000)
128 #define INTC_IPRH_INT58 (0x04000000)
129 #define INTC_IPRH_INT59 (0x08000000)
130 #define INTC_IPRH_INT60 (0x10000000)
131 #define INTC_IPRH_INT61 (0x20000000)
132 #define INTC_IPRH_INT62 (0x40000000)
133 #define INTC_IPRH_INT63 (0x80000000)
135 /* Bit definitions and macros for IPRL */
136 #define INTC_IPRL_INT0 (0x00000001)
137 #define INTC_IPRL_INT1 (0x00000002)
138 #define INTC_IPRL_INT2 (0x00000004)
139 #define INTC_IPRL_INT3 (0x00000008)
140 #define INTC_IPRL_INT4 (0x00000010)
141 #define INTC_IPRL_INT5 (0x00000020)
142 #define INTC_IPRL_INT6 (0x00000040)
143 #define INTC_IPRL_INT7 (0x00000080)
144 #define INTC_IPRL_INT8 (0x00000100)
145 #define INTC_IPRL_INT9 (0x00000200)
146 #define INTC_IPRL_INT10 (0x00000400)
147 #define INTC_IPRL_INT11 (0x00000800)
148 #define INTC_IPRL_INT12 (0x00001000)
149 #define INTC_IPRL_INT13 (0x00002000)
150 #define INTC_IPRL_INT14 (0x00004000)
151 #define INTC_IPRL_INT15 (0x00008000)
152 #define INTC_IPRL_INT16 (0x00010000)
153 #define INTC_IPRL_INT17 (0x00020000)
154 #define INTC_IPRL_INT18 (0x00040000)
155 #define INTC_IPRL_INT19 (0x00080000)
156 #define INTC_IPRL_INT20 (0x00100000)
157 #define INTC_IPRL_INT21 (0x00200000)
158 #define INTC_IPRL_INT22 (0x00400000)
159 #define INTC_IPRL_INT23 (0x00800000)
160 #define INTC_IPRL_INT24 (0x01000000)
161 #define INTC_IPRL_INT25 (0x02000000)
162 #define INTC_IPRL_INT26 (0x04000000)
163 #define INTC_IPRL_INT27 (0x08000000)
164 #define INTC_IPRL_INT28 (0x10000000)
165 #define INTC_IPRL_INT29 (0x20000000)
166 #define INTC_IPRL_INT30 (0x40000000)
167 #define INTC_IPRL_INT31 (0x80000000)
169 /* Bit definitions and macros for IMRH */
170 #define INTC_IMRH_INT_MASK32 (0x00000001)
171 #define INTC_IMRH_INT_MASK33 (0x00000002)
172 #define INTC_IMRH_INT_MASK34 (0x00000004)
173 #define INTC_IMRH_INT_MASK35 (0x00000008)
174 #define INTC_IMRH_INT_MASK36 (0x00000010)
175 #define INTC_IMRH_INT_MASK37 (0x00000020)
176 #define INTC_IMRH_INT_MASK38 (0x00000040)
177 #define INTC_IMRH_INT_MASK39 (0x00000080)
178 #define INTC_IMRH_INT_MASK40 (0x00000100)
179 #define INTC_IMRH_INT_MASK41 (0x00000200)
180 #define INTC_IMRH_INT_MASK42 (0x00000400)
181 #define INTC_IMRH_INT_MASK43 (0x00000800)
182 #define INTC_IMRH_INT_MASK44 (0x00001000)
183 #define INTC_IMRH_INT_MASK45 (0x00002000)
184 #define INTC_IMRH_INT_MASK46 (0x00004000)
185 #define INTC_IMRH_INT_MASK47 (0x00008000)
186 #define INTC_IMRH_INT_MASK48 (0x00010000)
187 #define INTC_IMRH_INT_MASK49 (0x00020000)
188 #define INTC_IMRH_INT_MASK50 (0x00040000)
189 #define INTC_IMRH_INT_MASK51 (0x00080000)
190 #define INTC_IMRH_INT_MASK52 (0x00100000)
191 #define INTC_IMRH_INT_MASK53 (0x00200000)
192 #define INTC_IMRH_INT_MASK54 (0x00400000)
193 #define INTC_IMRH_INT_MASK55 (0x00800000)
194 #define INTC_IMRH_INT_MASK56 (0x01000000)
195 #define INTC_IMRH_INT_MASK57 (0x02000000)
196 #define INTC_IMRH_INT_MASK58 (0x04000000)
197 #define INTC_IMRH_INT_MASK59 (0x08000000)
198 #define INTC_IMRH_INT_MASK60 (0x10000000)
199 #define INTC_IMRH_INT_MASK61 (0x20000000)
200 #define INTC_IMRH_INT_MASK62 (0x40000000)
201 #define INTC_IMRH_INT_MASK63 (0x80000000)
203 /* Bit definitions and macros for IMRL */
204 #define INTC_IMRL_INT_MASK0 (0x00000001)
205 #define INTC_IMRL_INT_MASK1 (0x00000002)
206 #define INTC_IMRL_INT_MASK2 (0x00000004)
207 #define INTC_IMRL_INT_MASK3 (0x00000008)
208 #define INTC_IMRL_INT_MASK4 (0x00000010)
209 #define INTC_IMRL_INT_MASK5 (0x00000020)
210 #define INTC_IMRL_INT_MASK6 (0x00000040)
211 #define INTC_IMRL_INT_MASK7 (0x00000080)
212 #define INTC_IMRL_INT_MASK8 (0x00000100)
213 #define INTC_IMRL_INT_MASK9 (0x00000200)
214 #define INTC_IMRL_INT_MASK10 (0x00000400)
215 #define INTC_IMRL_INT_MASK11 (0x00000800)
216 #define INTC_IMRL_INT_MASK12 (0x00001000)
217 #define INTC_IMRL_INT_MASK13 (0x00002000)
218 #define INTC_IMRL_INT_MASK14 (0x00004000)
219 #define INTC_IMRL_INT_MASK15 (0x00008000)
220 #define INTC_IMRL_INT_MASK16 (0x00010000)
221 #define INTC_IMRL_INT_MASK17 (0x00020000)
222 #define INTC_IMRL_INT_MASK18 (0x00040000)
223 #define INTC_IMRL_INT_MASK19 (0x00080000)
224 #define INTC_IMRL_INT_MASK20 (0x00100000)
225 #define INTC_IMRL_INT_MASK21 (0x00200000)
226 #define INTC_IMRL_INT_MASK22 (0x00400000)
227 #define INTC_IMRL_INT_MASK23 (0x00800000)
228 #define INTC_IMRL_INT_MASK24 (0x01000000)
229 #define INTC_IMRL_INT_MASK25 (0x02000000)
230 #define INTC_IMRL_INT_MASK26 (0x04000000)
231 #define INTC_IMRL_INT_MASK27 (0x08000000)
232 #define INTC_IMRL_INT_MASK28 (0x10000000)
233 #define INTC_IMRL_INT_MASK29 (0x20000000)
234 #define INTC_IMRL_INT_MASK30 (0x40000000)
235 #define INTC_IMRL_INT_MASK31 (0x80000000)
237 /* Bit definitions and macros for INTFRCH */
238 #define INTC_INTFRCH_INTFRC32 (0x00000001)
239 #define INTC_INTFRCH_INTFRC33 (0x00000002)
240 #define INTC_INTFRCH_INTFRC34 (0x00000004)
241 #define INTC_INTFRCH_INTFRC35 (0x00000008)
242 #define INTC_INTFRCH_INTFRC36 (0x00000010)
243 #define INTC_INTFRCH_INTFRC37 (0x00000020)
244 #define INTC_INTFRCH_INTFRC38 (0x00000040)
245 #define INTC_INTFRCH_INTFRC39 (0x00000080)
246 #define INTC_INTFRCH_INTFRC40 (0x00000100)
247 #define INTC_INTFRCH_INTFRC41 (0x00000200)
248 #define INTC_INTFRCH_INTFRC42 (0x00000400)
249 #define INTC_INTFRCH_INTFRC43 (0x00000800)
250 #define INTC_INTFRCH_INTFRC44 (0x00001000)
251 #define INTC_INTFRCH_INTFRC45 (0x00002000)
252 #define INTC_INTFRCH_INTFRC46 (0x00004000)
253 #define INTC_INTFRCH_INTFRC47 (0x00008000)
254 #define INTC_INTFRCH_INTFRC48 (0x00010000)
255 #define INTC_INTFRCH_INTFRC49 (0x00020000)
256 #define INTC_INTFRCH_INTFRC50 (0x00040000)
257 #define INTC_INTFRCH_INTFRC51 (0x00080000)
258 #define INTC_INTFRCH_INTFRC52 (0x00100000)
259 #define INTC_INTFRCH_INTFRC53 (0x00200000)
260 #define INTC_INTFRCH_INTFRC54 (0x00400000)
261 #define INTC_INTFRCH_INTFRC55 (0x00800000)
262 #define INTC_INTFRCH_INTFRC56 (0x01000000)
263 #define INTC_INTFRCH_INTFRC57 (0x02000000)
264 #define INTC_INTFRCH_INTFRC58 (0x04000000)
265 #define INTC_INTFRCH_INTFRC59 (0x08000000)
266 #define INTC_INTFRCH_INTFRC60 (0x10000000)
267 #define INTC_INTFRCH_INTFRC61 (0x20000000)
268 #define INTC_INTFRCH_INTFRC62 (0x40000000)
269 #define INTC_INTFRCH_INTFRC63 (0x80000000)
271 /* Bit definitions and macros for INTFRCL */
272 #define INTC_INTFRCL_INTFRC0 (0x00000001)
273 #define INTC_INTFRCL_INTFRC1 (0x00000002)
274 #define INTC_INTFRCL_INTFRC2 (0x00000004)
275 #define INTC_INTFRCL_INTFRC3 (0x00000008)
276 #define INTC_INTFRCL_INTFRC4 (0x00000010)
277 #define INTC_INTFRCL_INTFRC5 (0x00000020)
278 #define INTC_INTFRCL_INTFRC6 (0x00000040)
279 #define INTC_INTFRCL_INTFRC7 (0x00000080)
280 #define INTC_INTFRCL_INTFRC8 (0x00000100)
281 #define INTC_INTFRCL_INTFRC9 (0x00000200)
282 #define INTC_INTFRCL_INTFRC10 (0x00000400)
283 #define INTC_INTFRCL_INTFRC11 (0x00000800)
284 #define INTC_INTFRCL_INTFRC12 (0x00001000)
285 #define INTC_INTFRCL_INTFRC13 (0x00002000)
286 #define INTC_INTFRCL_INTFRC14 (0x00004000)
287 #define INTC_INTFRCL_INTFRC15 (0x00008000)
288 #define INTC_INTFRCL_INTFRC16 (0x00010000)
289 #define INTC_INTFRCL_INTFRC17 (0x00020000)
290 #define INTC_INTFRCL_INTFRC18 (0x00040000)
291 #define INTC_INTFRCL_INTFRC19 (0x00080000)
292 #define INTC_INTFRCL_INTFRC20 (0x00100000)
293 #define INTC_INTFRCL_INTFRC21 (0x00200000)
294 #define INTC_INTFRCL_INTFRC22 (0x00400000)
295 #define INTC_INTFRCL_INTFRC23 (0x00800000)
296 #define INTC_INTFRCL_INTFRC24 (0x01000000)
297 #define INTC_INTFRCL_INTFRC25 (0x02000000)
298 #define INTC_INTFRCL_INTFRC26 (0x04000000)
299 #define INTC_INTFRCL_INTFRC27 (0x08000000)
300 #define INTC_INTFRCL_INTFRC28 (0x10000000)
301 #define INTC_INTFRCL_INTFRC29 (0x20000000)
302 #define INTC_INTFRCL_INTFRC30 (0x40000000)
303 #define INTC_INTFRCL_INTFRC31 (0x80000000)
305 /* Bit definitions and macros for ICONFIG */
306 #define INTC_ICONFIG_EMASK (0x0020)
307 #define INTC_ICONFIG_ELVLPRI1 (0x0200)
308 #define INTC_ICONFIG_ELVLPRI2 (0x0400)
309 #define INTC_ICONFIG_ELVLPRI3 (0x0800)
310 #define INTC_ICONFIG_ELVLPRI4 (0x1000)
311 #define INTC_ICONFIG_ELVLPRI5 (0x2000)
312 #define INTC_ICONFIG_ELVLPRI6 (0x4000)
313 #define INTC_ICONFIG_ELVLPRI7 (0x8000)
315 /* Bit definitions and macros for SIMR */
316 #define INTC_SIMR_SIMR(x) (((x)&0x7F))
318 /* Bit definitions and macros for CIMR */
319 #define INTC_CIMR_CIMR(x) (((x)&0x7F))
321 /* Bit definitions and macros for CLMASK */
322 #define INTC_CLMASK_CLMASK(x) (((x)&0x0F))
324 /* Bit definitions and macros for SLMASK */
325 #define INTC_SLMASK_SLMASK(x) (((x)&0x0F))
327 /* Bit definitions and macros for ICR group */
328 #define INTC_ICR_IL(x) (((x)&0x07))
330 /*********************************************************************
331 * Reset Controller Module (RCM)
332 *********************************************************************/
334 /* Bit definitions and macros for RCR */
335 #define RCM_RCR_FRCRSTOUT (0x40)
336 #define RCM_RCR_SOFTRST (0x80)
338 /* Bit definitions and macros for RSR */
339 #define RCM_RSR_LOL (0x01)
340 #define RCM_RSR_WDR_CORE (0x02)
341 #define RCM_RSR_EXT (0x04)
342 #define RCM_RSR_POR (0x08)
343 #define RCM_RSR_SOFT (0x20)
345 /*********************************************************************
346 * Chip Configuration Module (CCM)
347 *********************************************************************/
349 /* Bit definitions and macros for CCR */
350 #define CCM_CCR_DRAMSEL (0x0100)
351 #define CCM_CCR_CSC_MASK (0xFF3F)
352 #define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
353 #define CCM_CCR_CSC_FBCS5_A22 (0x0080)
354 #define CCM_CCR_CSC_FB_A23_A22 (0x0040)
355 #define CCM_CCR_LIMP (0x0020)
356 #define CCM_CCR_LOAD (0x0010)
357 #define CCM_CCR_BOOTPS_MASK (0xFFF3)
358 #define CCM_CCR_BOOTPS_PS16 (0x0008)
359 #define CCM_CCR_BOOTPS_PS8 (0x0004)
360 #define CCM_CCR_BOOTPS_PS32 (0x0000)
361 #define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
363 /* Bit definitions and macros for RCON */
364 #define CCM_RCON_CSC_MASK (0xFF3F)
365 #define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
366 #define CCM_RCON_CSC_FBCS5_A22 (0x0080)
367 #define CCM_RCON_CSC_FB_A23_A22 (0x0040)
368 #define CCM_RCON_LIMP (0x0020)
369 #define CCM_RCON_LOAD (0x0010)
370 #define CCM_RCON_BOOTPS_MASK (0xFFF3)
371 #define CCM_RCON_BOOTPS_PS16 (0x0008)
372 #define CCM_RCON_BOOTPS_PS8 (0x0004)
373 #define CCM_RCON_BOOTPS_PS32 (0x0000)
374 #define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
376 /* Bit definitions and macros for CIR */
377 #define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
378 #define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
379 #define CCM_CIR_PIN_MASK (0xFFC0)
380 #define CCM_CIR_PRN_MASK (0x003F)
381 #define CCM_CIR_PIN_MCF52277 (0x0000)
383 /* Bit definitions and macros for MISCCR */
384 #define CCM_MISCCR_RTCSRC (0x4000)
385 #define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
386 #define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
388 #define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
389 #define CCM_MISCCR_BMT_65536 (0)
390 #define CCM_MISCCR_BMT_32768 (1)
391 #define CCM_MISCCR_BMT_16384 (2)
392 #define CCM_MISCCR_BMT_8192 (3)
393 #define CCM_MISCCR_BMT_4096 (4)
394 #define CCM_MISCCR_BMT_2048 (5)
395 #define CCM_MISCCR_BMT_1024 (6)
396 #define CCM_MISCCR_BMT_512 (7)
398 #define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
399 #define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
400 #define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
401 #define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
402 #define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
403 #define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
404 #define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
406 /* Bit definitions and macros for CDR */
407 #define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
408 #define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
409 #define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
411 /* Bit definitions and macros for UOCSR */
412 #define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
413 #define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
414 #define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
415 #define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
416 #define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
417 #define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
418 #define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
419 #define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
420 #define CCM_UOCSR_SEND (0x0010) /* Session end */
421 #define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
422 #define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
423 #define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
425 /*********************************************************************
426 * General Purpose I/O Module (GPIO)
427 *********************************************************************/
428 /* Bit definitions and macros for PAR_BE */
429 #define GPIO_PAR_BE_MASK (0x0F)
430 #define GPIO_PAR_BE_BE3_BE3 (0x08)
431 #define GPIO_PAR_BE_BE3_GPIO (0x00)
432 #define GPIO_PAR_BE_BE2_BE2 (0x04)
433 #define GPIO_PAR_BE_BE2_GPIO (0x00)
434 #define GPIO_PAR_BE_BE1_BE1 (0x02)
435 #define GPIO_PAR_BE_BE1_GPIO (0x00)
436 #define GPIO_PAR_BE_BE0_BE0 (0x01)
437 #define GPIO_PAR_BE_BE0_GPIO (0x00)
439 /* Bit definitions and macros for PAR_CS */
440 #define GPIO_PAR_CS_CS3 (0x10)
441 #define GPIO_PAR_CS_CS2 (0x08)
442 #define GPIO_PAR_CS_CS1_FBCS1 (0x06)
443 #define GPIO_PAR_CS_CS1_SDCS1 (0x04)
444 #define GPIO_PAR_CS_CS1_GPIO (0x00)
445 #define GPIO_PAR_CS_CS0 (0x01)
447 /* Bit definitions and macros for PAR_FBCTL */
448 #define GPIO_PAR_FBCTL_OE (0x80)
449 #define GPIO_PAR_FBCTL_TA (0x40)
450 #define GPIO_PAR_FBCTL_RW (0x20)
451 #define GPIO_PAR_FBCTL_TS_MASK (0xE7)
452 #define GPIO_PAR_FBCTL_TS_FBTS (0x18)
453 #define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
454 #define GPIO_PAR_FBCTL_TS_GPIO (0x00)
456 /* Bit definitions and macros for PAR_FECI2C */
457 #define GPIO_PAR_I2C_SCL_MASK (0xF3)
458 #define GPIO_PAR_I2C_SCL_SCL (0x0C)
459 #define GPIO_PAR_I2C_SCL_CANTXD (0x08)
460 #define GPIO_PAR_I2C_SCL_U2TXD (0x04)
461 #define GPIO_PAR_I2C_SCL_GPIO (0x00)
463 #define GPIO_PAR_I2C_SDA_MASK (0xFC)
464 #define GPIO_PAR_I2C_SDA_SDA (0x03)
465 #define GPIO_PAR_I2C_SDA_CANRXD (0x02)
466 #define GPIO_PAR_I2C_SDA_U2RXD (0x01)
467 #define GPIO_PAR_I2C_SDA_GPIO (0x00)
469 /* Bit definitions and macros for PAR_UART */
470 #define GPIO_PAR_UART_U1CTS_MASK (0x3FFF)
471 #define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
472 #define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
473 #define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
474 #define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
476 #define GPIO_PAR_UART_U1RTS_MASK (0xCFFF)
477 #define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
478 #define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
479 #define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
480 #define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
482 #define GPIO_PAR_UART_U1RXD_MASK (0xF3FF)
483 #define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
484 #define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
485 #define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
487 #define GPIO_PAR_UART_U1TXD_MASK (0xFCFF)
488 #define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
489 #define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
490 #define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
492 #define GPIO_PAR_UART_U0CTS_MASK (0xFF3F)
493 #define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
494 #define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
495 #define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
496 #define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
498 #define GPIO_PAR_UART_U0RTS_MASK (0xFFCF)
499 #define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
500 #define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
501 #define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
502 #define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
504 #define GPIO_PAR_UART_U0RXD_MASK (0xFFF3)
505 #define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
506 #define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
507 #define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
509 #define GPIO_PAR_UART_U0TXD_MASK (0xFFFC)
510 #define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
511 #define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
512 #define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
514 /* Bit definitions and macros for PAR_DSPI */
515 #define GPIO_PAR_DSPI_PCS0_MASK (0x3F)
516 #define GPIO_PAR_DSPI_PCS0_PCS0 (0x80)
517 #define GPIO_PAR_DSPI_PCS0_U2RTS (0x40)
518 #define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
519 #define GPIO_PAR_DSPI_SIN_MASK (0xCF)
520 #define GPIO_PAR_DSPI_SIN_SIN (0x30)
521 #define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
522 #define GPIO_PAR_DSPI_SIN_GPIO (0x00)
523 #define GPIO_PAR_DSPI_SOUT_MASK (0xF3)
524 #define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
525 #define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
526 #define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
527 #define GPIO_PAR_DSPI_SCK_MASK (0xFC)
528 #define GPIO_PAR_DSPI_SCK_SCK (0x03)
529 #define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
530 #define GPIO_PAR_DSPI_SCK_GPIO (0x00)
532 /* Bit definitions and macros for PAR_TIMER */
533 #define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
534 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
535 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
536 #define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
537 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
538 #define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
539 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
540 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
541 #define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
542 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
543 #define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
544 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
545 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
546 #define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
547 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
548 #define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
549 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
550 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
551 #define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
552 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
554 /* Bit definitions and macros for GPIO_PAR_LCDCTL */
555 #define GPIO_PAR_LCDCTL_ACDOE_MASK (0xE7)
556 #define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
557 #define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
558 #define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
559 #define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
560 #define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
561 #define GPIO_PAR_LCDCTL_LSCLK (0x01)
563 /* Bit definitions and macros for PAR_IRQ */
564 #define GPIO_PAR_IRQ_IRQ4_MASK (0xF3)
565 #define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
566 #define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
567 #define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
568 #define GPIO_PAR_IRQ_IRQ1_MASK (0xFC)
569 #define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
570 #define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
571 #define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
572 #define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
574 /* Bit definitions and macros for GPIO_PAR_LCDH */
575 #define GPIO_PAR_LCDH_LD17_MASK (0xFFFFF3FF)
576 #define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
577 #define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
578 #define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
580 #define GPIO_PAR_LCDH_LD16_MASK (0xFFFFFCFF)
581 #define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
582 #define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
583 #define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
585 #define GPIO_PAR_LCDH_LD15_MASK (0xFFFFFF3F)
586 #define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
587 #define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
588 #define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
590 #define GPIO_PAR_LCDH_LD14_MASK (0xFFFFFFCF)
591 #define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
592 #define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
593 #define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
595 #define GPIO_PAR_LCDH_LD13_MASK (0xFFFFFFF3)
596 #define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
597 #define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
598 #define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
600 #define GPIO_PAR_LCDH_LD12_MASK (0xFFFFFFFC)
601 #define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
602 #define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
603 #define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
605 /* Bit definitions and macros for GPIO_PAR_LCDL */
606 #define GPIO_PAR_LCDL_LD11_MASK (0x3FFFFFFF)
607 #define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
608 #define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
609 #define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
611 #define GPIO_PAR_LCDL_LD10_MASK (0xCFFFFFFF)
612 #define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
613 #define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
614 #define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
616 #define GPIO_PAR_LCDL_LD9_MASK (0xF3FFFFFF)
617 #define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
618 #define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
619 #define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
621 #define GPIO_PAR_LCDL_LD8_MASK (0xFCFFFFFF)
622 #define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
623 #define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
624 #define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
626 #define GPIO_PAR_LCDL_LD7_MASK (0xFF3FFFFF)
627 #define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
628 #define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
629 #define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
631 #define GPIO_PAR_LCDL_LD6_MASK (0xFFCFFFFF)
632 #define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
633 #define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
634 #define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
636 #define GPIO_PAR_LCDL_LD5_MASK (0xFFF3FFFF)
637 #define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
638 #define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
639 #define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
641 #define GPIO_PAR_LCDL_LD4_MASK (0xFFFCFFFF)
642 #define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
643 #define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
644 #define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
646 #define GPIO_PAR_LCDL_LD3_MASK (0xFFFF3FFF)
647 #define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
648 #define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
649 #define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
651 #define GPIO_PAR_LCDL_LD2_MASK (0xFFFFCFFF)
652 #define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
653 #define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
654 #define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
656 #define GPIO_PAR_LCDL_LD1_MASK (0xFFFFF3FF)
657 #define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
658 #define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
659 #define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
661 #define GPIO_PAR_LCDL_LD0_MASK (0xFFFFFCFF)
662 #define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
663 #define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
664 #define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
666 /* Bit definitions and macros for MSCR_FB */
667 #define GPIO_MSCR_FB_DUPPER_MASK (0xCF)
668 #define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
669 #define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
670 #define GPIO_MSCR_FB_DUPPER_OD (0x10)
671 #define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
673 #define GPIO_MSCR_FB_DLOWER_MASK (0xF3)
674 #define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
675 #define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
676 #define GPIO_MSCR_FB_DLOWER_OD (0x04)
677 #define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
679 #define GPIO_MSCR_FB_ADDRCTL_MASK (0xFC)
680 #define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
681 #define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
682 #define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
683 #define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
685 /* Bit definitions and macros for MSCR_SDRAM */
686 #define GPIO_MSCR_SDRAM_SDCLKB_MASK (0xCF)
687 #define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
688 #define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
689 #define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
690 #define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
692 #define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
693 #define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
694 #define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
695 #define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
696 #define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
698 #define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
699 #define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
700 #define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
701 #define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
702 #define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
704 /* Bit definitions and macros for Drive Strength Control */
705 #define DSCR_LOAD_50PF (0x03)
706 #define DSCR_LOAD_30PF (0x02)
707 #define DSCR_LOAD_20PF (0x01)
708 #define DSCR_LOAD_10PF (0x00)
710 /*********************************************************************
711 * SDRAM Controller (SDRAMC)
712 *********************************************************************/
714 /* Bit definitions and macros for SDMR */
715 #define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
716 #define SDRAMC_SDMR_CMD (0x00010000) /* Command */
717 #define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
718 #define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
719 #define SDRAMC_SDMR_BK_LMR (0x00000000)
720 #define SDRAMC_SDMR_BK_LEMR (0x40000000)
722 /* Bit definitions and macros for SDCR */
723 #define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
724 #define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
725 #define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
726 #define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
727 #define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
728 #define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
729 #define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
730 #define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
731 #define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
732 #define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
733 #define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
734 #define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
735 #define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
736 #define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
738 /* Bit definitions and macros for SDCFG1 */
739 #define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
740 #define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
741 #define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
742 #define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
743 #define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
744 #define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
745 #define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
747 /* Bit definitions and macros for SDCFG2 */
748 #define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
749 #define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
750 #define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
751 #define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
753 /* Bit definitions and macros for SDCS group */
754 #define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
755 #define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
756 #define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
757 #define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
758 #define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
759 #define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
760 #define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
761 #define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
762 #define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
763 #define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
764 #define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
765 #define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
766 #define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
767 #define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
768 #define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
769 #define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
770 #define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
772 /*********************************************************************
773 * Phase Locked Loop (PLL)
774 *********************************************************************/
776 /* Bit definitions and macros for PCR */
777 #define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
778 #define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
779 #define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
780 #define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
781 #define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
782 #define PLL_PCR_PFDR_MASK (0x000F0000)
783 #define PLL_PCR_OUTDIV5_MASK (0x000F0000)
784 #define PLL_PCR_OUTDIV3_MASK (0x00000F00)
785 #define PLL_PCR_OUTDIV2_MASK (0x000000F0)
786 #define PLL_PCR_OUTDIV1_MASK (0x0000000F)
788 /* Bit definitions and macros for PSR */
789 #define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
790 #define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
791 #define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
792 #define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
794 /********************************************************************/
796 #endif /* __MCF5227X__ */