2 * ColdFire Internal Memory Map and Defines
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap_5227x.h>
31 #include <asm/m5227x.h>
33 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
35 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
38 #define CONFIG_SYS_LCD_BASE (MMAP_LCD)
43 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
44 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
45 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
46 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
47 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
48 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
49 #define CONFIG_SYS_TMRINTR_PRI (6)
50 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
54 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
55 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
56 #define CONFIG_SYS_PIT_PRESCALE (6)
59 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
60 #define CONFIG_SYS_NUM_IRQS (128)
61 #endif /* CONFIG_M52277 */
64 #include <asm/immap_5235.h>
65 #include <asm/m5235.h>
67 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
68 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
72 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
73 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
74 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
75 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
76 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
77 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
78 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
79 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
83 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
84 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
85 #define CONFIG_SYS_PIT_PRESCALE (6)
88 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
89 #define CONFIG_SYS_NUM_IRQS (128)
90 #endif /* CONFIG_M5235 */
93 #include <asm/immap_5249.h>
94 #include <asm/m5249.h>
96 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
98 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
99 #define CONFIG_SYS_NUM_IRQS (64)
103 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
104 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
105 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
106 #define CONFIG_SYS_TMRINTR_NO (31)
107 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
108 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
109 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
110 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
112 #endif /* CONFIG_M5249 */
115 #include <asm/immap_5253.h>
116 #include <asm/m5249.h>
117 #include <asm/m5253.h>
119 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
121 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
122 #define CONFIG_SYS_NUM_IRQS (64)
126 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
127 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
128 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
129 #define CONFIG_SYS_TMRINTR_NO (27)
130 #define CONFIG_SYS_TMRINTR_MASK (0x00000400)
131 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
132 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
133 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
135 #endif /* CONFIG_M5253 */
138 #include <asm/immap_5271.h>
139 #include <asm/m5271.h>
141 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
142 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
146 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
147 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
148 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
149 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
150 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
151 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
152 #define CONFIG_SYS_TMRINTR_PRI (0) /* Level must include inorder to work */
153 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
156 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
157 #define CONFIG_SYS_NUM_IRQS (128)
158 #endif /* CONFIG_M5271 */
161 #include <asm/immap_5272.h>
162 #include <asm/m5272.h>
164 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
165 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
167 #define CONFIG_SYS_INTR_BASE (MMAP_INTC)
168 #define CONFIG_SYS_NUM_IRQS (64)
172 #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
173 #define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
174 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
175 #define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
176 #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
177 #define CONFIG_SYS_TMRINTR_PEND (0)
178 #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
179 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
181 #endif /* CONFIG_M5272 */
184 #include <asm/immap_5275.h>
185 #include <asm/m5275.h>
187 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
188 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
189 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
191 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
192 #define CONFIG_SYS_NUM_IRQS (192)
196 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
197 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
198 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
199 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
200 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
201 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
202 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
203 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
205 #endif /* CONFIG_M5275 */
208 #include <asm/immap_5282.h>
209 #include <asm/m5282.h>
211 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
212 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
214 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
215 #define CONFIG_SYS_NUM_IRQS (128)
219 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
220 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
221 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
222 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
223 #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
224 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
225 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
226 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
228 #endif /* CONFIG_M5282 */
230 #if defined(CONFIG_MCF5301x)
231 #include <asm/immap_5301x.h>
232 #include <asm/m5301x.h>
234 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
235 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
236 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
238 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
242 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
243 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
244 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
245 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
246 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
247 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
248 #define CONFIG_SYS_TMRINTR_PRI (6)
249 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
253 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
254 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
255 #define CONFIG_SYS_PIT_PRESCALE (6)
258 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
259 #define CONFIG_SYS_NUM_IRQS (128)
260 #endif /* CONFIG_M5301x */
262 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
263 #include <asm/immap_5329.h>
264 #include <asm/m5329.h>
266 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
267 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
268 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
272 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
273 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
274 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
275 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
276 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
277 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
278 #define CONFIG_SYS_TMRINTR_PRI (6)
279 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
283 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
284 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
285 #define CONFIG_SYS_PIT_PRESCALE (6)
288 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
289 #define CONFIG_SYS_NUM_IRQS (128)
290 #endif /* CONFIG_M5329 && CONFIG_M5373 */
292 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
293 #include <asm/immap_5445x.h>
294 #include <asm/m5445x.h>
296 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
297 #if defined(CONFIG_M54455EVB)
298 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
301 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
303 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
307 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
308 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
309 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
310 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
311 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
312 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
313 #define CONFIG_SYS_TMRINTR_PRI (6)
314 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
318 #define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
319 #define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
320 #define CONFIG_SYS_PIT_PRESCALE (6)
323 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
324 #define CONFIG_SYS_NUM_IRQS (128)
327 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
328 #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
329 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
330 #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
332 #endif /* CONFIG_M54451 || CONFIG_M54455 */
335 #include <asm/immap_547x_8x.h>
336 #include <asm/m547x_8x.h>
338 #ifdef CONFIG_FSLDMAFEC
339 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
340 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
342 #define FEC0_RX_TASK 0
343 #define FEC0_TX_TASK 1
344 #define FEC0_RX_PRIORITY 6
345 #define FEC0_TX_PRIORITY 7
346 #define FEC0_RX_INIT 16
347 #define FEC0_TX_INIT 17
348 #define FEC1_RX_TASK 2
349 #define FEC1_TX_TASK 3
350 #define FEC1_RX_PRIORITY 6
351 #define FEC1_TX_PRIORITY 7
352 #define FEC1_RX_INIT 30
353 #define FEC1_TX_INIT 31
356 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
359 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
360 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
361 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
362 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
363 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
364 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
365 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
366 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
369 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
370 #define CONFIG_SYS_NUM_IRQS (128)
373 #define CONFIG_SYS_PCI_BAR0 (0x40000000)
374 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
375 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
376 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
378 #endif /* CONFIG_M547x */
381 #include <asm/immap_547x_8x.h>
382 #include <asm/m547x_8x.h>
384 #ifdef CONFIG_FSLDMAFEC
385 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
386 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
388 #define FEC0_RX_TASK 0
389 #define FEC0_TX_TASK 1
390 #define FEC0_RX_PRIORITY 6
391 #define FEC0_TX_PRIORITY 7
392 #define FEC0_RX_INIT 16
393 #define FEC0_TX_INIT 17
394 #define FEC1_RX_TASK 2
395 #define FEC1_TX_TASK 3
396 #define FEC1_RX_PRIORITY 6
397 #define FEC1_TX_PRIORITY 7
398 #define FEC1_RX_INIT 30
399 #define FEC1_TX_INIT 31
402 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
406 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
407 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
408 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
409 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
410 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
411 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
412 #define CONFIG_SYS_TMRINTR_PRI (0x1E)
413 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
416 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
417 #define CONFIG_SYS_NUM_IRQS (128)
420 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
421 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
422 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
423 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
425 #endif /* CONFIG_M548x */
427 #endif /* __IMMAP_H */