2 * fec.h -- Fast Ethernet Controller definitions
4 * Some definitions copied from commproc.h for MPC8xx:
5 * MPC8xx Communication Processor Module.
6 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
8 * Add FEC Structure and definitions
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 /* Buffer descriptors used FEC.
36 typedef struct cpm_buf_desc {
37 ushort cbd_sc; /* Status and Control */
38 ushort cbd_datlen; /* Data length in buffer */
39 uint cbd_bufaddr; /* Buffer address in host memory */
42 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
43 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
44 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
45 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
46 #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
47 #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
48 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
49 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
50 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
51 #define BD_SC_BR ((ushort)0x0020) /* Break received */
52 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
53 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
54 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
55 #define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
57 /* Buffer descriptor control/status used by Ethernet receive.
59 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
60 #define BD_ENET_RX_RO1 ((ushort)0x4000)
61 #define BD_ENET_RX_WRAP ((ushort)0x2000)
62 #define BD_ENET_RX_INTR ((ushort)0x1000)
63 #define BD_ENET_RX_RO2 BD_ENET_RX_INTR
64 #define BD_ENET_RX_LAST ((ushort)0x0800)
65 #define BD_ENET_RX_FIRST ((ushort)0x0400)
66 #define BD_ENET_RX_MISS ((ushort)0x0100)
67 #define BD_ENET_RX_BC ((ushort)0x0080)
68 #define BD_ENET_RX_MC ((ushort)0x0040)
69 #define BD_ENET_RX_LG ((ushort)0x0020)
70 #define BD_ENET_RX_NO ((ushort)0x0010)
71 #define BD_ENET_RX_SH ((ushort)0x0008)
72 #define BD_ENET_RX_CR ((ushort)0x0004)
73 #define BD_ENET_RX_OV ((ushort)0x0002)
74 #define BD_ENET_RX_CL ((ushort)0x0001)
75 #define BD_ENET_RX_TR BD_ENET_RX_CL
76 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
78 /* Buffer descriptor control/status used by Ethernet transmit.
80 #define BD_ENET_TX_READY ((ushort)0x8000)
81 #define BD_ENET_TX_PAD ((ushort)0x4000)
82 #define BD_ENET_TX_TO1 BD_ENET_TX_PAD
83 #define BD_ENET_TX_WRAP ((ushort)0x2000)
84 #define BD_ENET_TX_INTR ((ushort)0x1000)
85 #define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
86 #define BD_ENET_TX_LAST ((ushort)0x0800)
87 #define BD_ENET_TX_TC ((ushort)0x0400)
88 #define BD_ENET_TX_DEF ((ushort)0x0200)
89 #define BD_ENET_TX_ABC BD_ENET_TX_DEF
90 #define BD_ENET_TX_HB ((ushort)0x0100)
91 #define BD_ENET_TX_LC ((ushort)0x0080)
92 #define BD_ENET_TX_RL ((ushort)0x0040)
93 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
94 #define BD_ENET_TX_UN ((ushort)0x0002)
95 #define BD_ENET_TX_CSL ((ushort)0x0001)
96 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
99 /*********************************************************************
101 * Fast Ethernet Controller (FEC)
103 *********************************************************************/
104 /* FEC private information */
114 cbd_t *rxbd; /* Rx BD */
115 cbd_t *txbd; /* Tx BD */
122 /* Register read/write struct */
165 u32 rmon_t_crc_align;
166 u32 rmon_t_undersize;
173 u32 rmon_t_p128to255;
174 u32 rmon_t_p256to511;
175 u32 rmon_t_p512to1023;
176 u32 rmon_t_p1024to2047;
177 u32 rmon_t_p_gte2048;
191 u32 ieee_t_octets_ok;
198 u32 rmon_r_crc_align;
199 u32 rmon_r_undersize;
206 u32 rmon_r_p128to255;
207 u32 rmon_r_p256to511;
208 u32 rmon_r_p512to1023;
209 u32 rmon_r_p1024to2047;
210 u32 rmon_r_p_gte2048;
219 u32 ieee_r_octets_ok;
222 /*********************************************************************
223 * Fast Ethernet Controller (FEC)
224 *********************************************************************/
225 /* Bit definitions and macros for FEC_EIR */
226 #define FEC_EIR_CLEAR_ALL (0xFFF80000)
227 #define FEC_EIR_HBERR (0x80000000)
228 #define FEC_EIR_BABR (0x40000000)
229 #define FEC_EIR_BABT (0x20000000)
230 #define FEC_EIR_GRA (0x10000000)
231 #define FEC_EIR_TXF (0x08000000)
232 #define FEC_EIR_TXB (0x04000000)
233 #define FEC_EIR_RXF (0x02000000)
234 #define FEC_EIR_RXB (0x01000000)
235 #define FEC_EIR_MII (0x00800000)
236 #define FEC_EIR_EBERR (0x00400000)
237 #define FEC_EIR_LC (0x00200000)
238 #define FEC_EIR_RL (0x00100000)
239 #define FEC_EIR_UN (0x00080000)
241 /* Bit definitions and macros for FEC_RDAR */
242 #define FEC_RDAR_R_DES_ACTIVE (0x01000000)
244 /* Bit definitions and macros for FEC_TDAR */
245 #define FEC_TDAR_X_DES_ACTIVE (0x01000000)
247 /* Bit definitions and macros for FEC_ECR */
248 #define FEC_ECR_ETHER_EN (0x00000002)
249 #define FEC_ECR_RESET (0x00000001)
251 /* Bit definitions and macros for FEC_MMFR */
252 #define FEC_MMFR_DATA(x) (((x)&0xFFFF))
253 #define FEC_MMFR_ST(x) (((x)&0x03)<<30)
254 #define FEC_MMFR_ST_01 (0x40000000)
255 #define FEC_MMFR_OP_RD (0x20000000)
256 #define FEC_MMFR_OP_WR (0x10000000)
257 #define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
258 #define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
259 #define FEC_MMFR_TA(x) (((x)&0x03)<<16)
260 #define FEC_MMFR_TA_10 (0x00020000)
262 /* Bit definitions and macros for FEC_MSCR */
263 #define FEC_MSCR_DIS_PREAMBLE (0x00000080)
264 #define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
266 /* Bit definitions and macros for FEC_MIBC */
267 #define FEC_MIBC_MIB_DISABLE (0x80000000)
268 #define FEC_MIBC_MIB_IDLE (0x40000000)
270 /* Bit definitions and macros for FEC_RCR */
271 #define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
272 #define FEC_RCR_FCE (0x00000020)
273 #define FEC_RCR_BC_REJ (0x00000010)
274 #define FEC_RCR_PROM (0x00000008)
275 #define FEC_RCR_MII_MODE (0x00000004)
276 #define FEC_RCR_DRT (0x00000002)
277 #define FEC_RCR_LOOP (0x00000001)
279 /* Bit definitions and macros for FEC_TCR */
280 #define FEC_TCR_RFC_PAUSE (0x00000010)
281 #define FEC_TCR_TFC_PAUSE (0x00000008)
282 #define FEC_TCR_FDEN (0x00000004)
283 #define FEC_TCR_HBC (0x00000002)
284 #define FEC_TCR_GTS (0x00000001)
286 /* Bit definitions and macros for FEC_PAUR */
287 #define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
288 #define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
290 /* Bit definitions and macros for FEC_OPD */
291 #define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
292 #define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
294 /* Bit definitions and macros for FEC_TFWR */
295 #define FEC_TFWR_X_WMRK(x) ((x)&0x03)
296 #define FEC_TFWR_X_WMRK_64 (0x01)
297 #define FEC_TFWR_X_WMRK_128 (0x02)
298 #define FEC_TFWR_X_WMRK_192 (0x03)
300 /* Bit definitions and macros for FEC_FRBR */
301 #define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
303 /* Bit definitions and macros for FEC_FRSR */
304 #define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
306 /* Bit definitions and macros for FEC_ERDSR */
307 #define FEC_ERDSR_R_DES_START(x)(((x)&0x3FFFFFFF)<<2)
309 /* Bit definitions and macros for FEC_ETDSR */
310 #define FEC_ETDSR_X_DES_START(x)(((x)&0x3FFFFFFF)<<2)
312 /* Bit definitions and macros for FEC_EMRBR */
313 #define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
315 #define FEC_RESET_DELAY 100
316 #define FEC_RX_TOUT 100
318 #endif /* CONFIG_MCFFEC */