2 * SSI Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /*********************************************************************
30 * Synchronous Serial Interface (SSI)
31 *********************************************************************/
55 /*********************************************************************
56 * Synchronous Serial Interface (SSI)
57 *********************************************************************/
59 /* Bit definitions and macros for SSI_CR */
60 #define SSI_CR_CIS (0x00000200)
61 #define SSI_CR_TCH (0x00000100)
62 #define SSI_CR_MCE (0x00000080)
63 #define SSI_CR_I2S_SLAVE (0x00000040)
64 #define SSI_CR_I2S_MASTER (0x00000020)
65 #define SSI_CR_I2S_NORMAL (0x00000000)
66 #define SSI_CR_SYN (0x00000010)
67 #define SSI_CR_NET (0x00000008)
68 #define SSI_CR_RE (0x00000004)
69 #define SSI_CR_TE (0x00000002)
70 #define SSI_CR_SSI_EN (0x00000001)
72 /* Bit definitions and macros for SSI_ISR */
73 #define SSI_ISR_CMDAU (0x00040000)
74 #define SSI_ISR_CMDDU (0x00020000)
75 #define SSI_ISR_RXT (0x00010000)
76 #define SSI_ISR_RDR1 (0x00008000)
77 #define SSI_ISR_RDR0 (0x00004000)
78 #define SSI_ISR_TDE1 (0x00002000)
79 #define SSI_ISR_TDE0 (0x00001000)
80 #define SSI_ISR_ROE1 (0x00000800)
81 #define SSI_ISR_ROE0 (0x00000400)
82 #define SSI_ISR_TUE1 (0x00000200)
83 #define SSI_ISR_TUE0 (0x00000100)
84 #define SSI_ISR_TFS (0x00000080)
85 #define SSI_ISR_RFS (0x00000040)
86 #define SSI_ISR_TLS (0x00000020)
87 #define SSI_ISR_RLS (0x00000010)
88 #define SSI_ISR_RFF1 (0x00000008)
89 #define SSI_ISR_RFF0 (0x00000004)
90 #define SSI_ISR_TFE1 (0x00000002)
91 #define SSI_ISR_TFE0 (0x00000001)
93 /* Bit definitions and macros for SSI_IER */
94 #define SSI_IER_RDMAE (0x00400000)
95 #define SSI_IER_RIE (0x00200000)
96 #define SSI_IER_TDMAE (0x00100000)
97 #define SSI_IER_TIE (0x00080000)
98 #define SSI_IER_CMDAU (0x00040000)
99 #define SSI_IER_CMDU (0x00020000)
100 #define SSI_IER_RXT (0x00010000)
101 #define SSI_IER_RDR1 (0x00008000)
102 #define SSI_IER_RDR0 (0x00004000)
103 #define SSI_IER_TDE1 (0x00002000)
104 #define SSI_IER_TDE0 (0x00001000)
105 #define SSI_IER_ROE1 (0x00000800)
106 #define SSI_IER_ROE0 (0x00000400)
107 #define SSI_IER_TUE1 (0x00000200)
108 #define SSI_IER_TUE0 (0x00000100)
109 #define SSI_IER_TFS (0x00000080)
110 #define SSI_IER_RFS (0x00000040)
111 #define SSI_IER_TLS (0x00000020)
112 #define SSI_IER_RLS (0x00000010)
113 #define SSI_IER_RFF1 (0x00000008)
114 #define SSI_IER_RFF0 (0x00000004)
115 #define SSI_IER_TFE1 (0x00000002)
116 #define SSI_IER_TFE0 (0x00000001)
118 /* Bit definitions and macros for SSI_TCR */
119 #define SSI_TCR_TXBIT0 (0x00000200)
120 #define SSI_TCR_TFEN1 (0x00000100)
121 #define SSI_TCR_TFEN0 (0x00000080)
122 #define SSI_TCR_TFDIR (0x00000040)
123 #define SSI_TCR_TXDIR (0x00000020)
124 #define SSI_TCR_TSHFD (0x00000010)
125 #define SSI_TCR_TSCKP (0x00000008)
126 #define SSI_TCR_TFSI (0x00000004)
127 #define SSI_TCR_TFSL (0x00000002)
128 #define SSI_TCR_TEFS (0x00000001)
130 /* Bit definitions and macros for SSI_RCR */
131 #define SSI_RCR_RXEXT (0x00000400)
132 #define SSI_RCR_RXBIT0 (0x00000200)
133 #define SSI_RCR_RFEN1 (0x00000100)
134 #define SSI_RCR_RFEN0 (0x00000080)
135 #define SSI_RCR_RSHFD (0x00000010)
136 #define SSI_RCR_RSCKP (0x00000008)
137 #define SSI_RCR_RFSI (0x00000004)
138 #define SSI_RCR_RFSL (0x00000002)
139 #define SSI_RCR_REFS (0x00000001)
141 /* Bit definitions and macros for SSI_CCR */
142 #define SSI_CCR_DIV2 (0x00040000)
143 #define SSI_CCR_PSR (0x00020000)
144 #define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
145 #define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
146 #define SSI_CCR_PM(x) ((x)&0x000000FF)
148 /* Bit definitions and macros for SSI_FCSR */
149 #define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
150 #define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
151 #define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
152 #define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
153 #define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
154 #define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
155 #define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
156 #define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
158 /* Bit definitions and macros for SSI_ACR */
159 #define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
160 #define SSI_ACR_WR (0x00000010)
161 #define SSI_ACR_RD (0x00000008)
162 #define SSI_ACR_TIF (0x00000004)
163 #define SSI_ACR_FV (0x00000002)
164 #define SSI_ACR_AC97EN (0x00000001)
166 /* Bit definitions and macros for SSI_ACADD */
167 #define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
169 /* Bit definitions and macros for SSI_ACDAT */
170 #define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
172 /* Bit definitions and macros for SSI_ATAG */
173 #define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
175 #endif /* __SSI_H__ */