2 * Cross Bar Switch Internal Memory Map
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #ifndef __CROSSBAR_H__
27 #define __CROSSBAR_H__
29 /*********************************************************************
30 * Cross-bar switch (XBS)
31 *********************************************************************/
33 u32 prs1; /* 0x100 Priority Register Slave 1 */
34 u32 res1[3]; /* 0x104 - 0F */
35 u32 crs1; /* 0x110 Control Register Slave 1 */
36 u32 res2[187]; /* 0x114 - 0x3FF */
38 u32 prs4; /* 0x400 Priority Register Slave 4 */
39 u32 res3[3]; /* 0x404 - 0F */
40 u32 crs4; /* 0x410 Control Register Slave 4 */
41 u32 res4[123]; /* 0x414 - 0x5FF */
43 u32 prs6; /* 0x600 Priority Register Slave 6 */
44 u32 res5[3]; /* 0x604 - 0F */
45 u32 crs6; /* 0x610 Control Register Slave 6 */
46 u32 res6[59]; /* 0x614 - 0x6FF */
48 u32 prs7; /* 0x700 Priority Register Slave 7 */
49 u32 res7[3]; /* 0x704 - 0F */
50 u32 crs7; /* 0x710 Control Register Slave 7 */
53 /* Bit definitions and macros for PRS group */
54 #define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
55 #define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
56 #define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
57 #define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
58 #define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
59 #define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
60 #define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
62 /* Bit definitions and macros for CRS group */
63 #define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
64 #define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
65 #define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
66 #define XBS_CRS_RO (0x80000000) /* Read Only */
68 #define XBS_CRS_PCTL_PARK_FIELD (0)
69 #define XBS_CRS_PCTL_PARK_ON_LAST (1)
70 #define XBS_CRS_PCTL_PARK_NONE (2)
71 #define XBS_CRS_PCTL_PARK_CORE (0)
72 #define XBS_CRS_PCTL_PARK_EDMA (1)
73 #define XBS_CRS_PCTL_PARK_FEC0 (2)
74 #define XBS_CRS_PCTL_PARK_FEC1 (3)
75 #define XBS_CRS_PCTL_PARK_PCI (5)
76 #define XBS_CRS_PCTL_PARK_USB (6)
77 #define XBS_CRS_PCTL_PARK_SBF (7)
79 #endif /* __CROSSBAR_H__ */