4 * This file is subject to the terms and conditions of the GNU Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Non-GPL License also available as part of VisualDSP++
10 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
12 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
14 * This file under source code control, please send bugs or changes to:
15 * dsptools.support@analog.com
19 #ifndef _DEF_BF561_EXTN_H
20 #define _DEF_BF561_EXTN_H
22 #define OFFSET_( x ) ((x) & 0x0000FFFF) /* define macro for offset */
23 /* Delay inserted for PLL transition */
24 #define PLL_DELAY 0x1000
26 #define L1_ISRAM 0xFFA00000
27 #define L1_ISRAM_END 0xFFA10000
28 #define DATA_BANKA_SRAM 0xFF800000
29 #define DATA_BANKA_SRAM_END 0xFF808000
30 #define DATA_BANKB_SRAM 0xFF900000
31 #define DATA_BANKB_SRAM_END 0xFF908000
32 #define SYSMMR_BASE 0xFFC00000
33 #define WDSIZE16 0x00000004
35 /* Event Vector Table Address */
36 #define EVT_EMULATION_ADDR 0xffe02000
37 #define EVT_RESET_ADDR 0xffe02004
38 #define EVT_NMI_ADDR 0xffe02008
39 #define EVT_EXCEPTION_ADDR 0xffe0200c
40 #define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
41 #define EVT_HARDWARE_ERROR_ADDR 0xffe02014
42 #define EVT_TIMER_ADDR 0xffe02018
43 #define EVT_IVG7_ADDR 0xffe0201c
44 #define EVT_IVG8_ADDR 0xffe02020
45 #define EVT_IVG9_ADDR 0xffe02024
46 #define EVT_IVG10_ADDR 0xffe02028
47 #define EVT_IVG11_ADDR 0xffe0202c
48 #define EVT_IVG12_ADDR 0xffe02030
49 #define EVT_IVG13_ADDR 0xffe02034
50 #define EVT_IVG14_ADDR 0xffe02038
51 #define EVT_IVG15_ADDR 0xffe0203c
52 #define EVT_OVERRIDE_ADDR 0xffe02100
54 /* IMASK Bit values */
55 #define IVG15_POS 0x00008000
56 #define IVG14_POS 0x00004000
57 #define IVG13_POS 0x00002000
58 #define IVG12_POS 0x00001000
59 #define IVG11_POS 0x00000800
60 #define IVG10_POS 0x00000400
61 #define IVG9_POS 0x00000200
62 #define IVG8_POS 0x00000100
63 #define IVG7_POS 0x00000080
64 #define IVGTMR_POS 0x00000040
65 #define IVGHW_POS 0x00000020
67 #define WDOG_TMR_DISABLE (0xAD << 4)
68 #define ICTL_RST 0x00000000
69 #define ICTL_NMI 0x00000002
70 #define ICTL_GP 0x00000004
71 #define ICTL_DISABLE 0x00000003
73 /* Watch Dog timer values setup */
74 #define WATCHDOG_DISABLE WDOG_TMR_DISABLE | ICTL_DISABLE
76 #endif /* _DEF_BF561_EXTN_H */