4 * Copyright (c) 2005-2007 Analog Devices Inc.
6 * This file is based on
7 * linux/arch/$(ARCH)/platform/$(PLATFORM)/irq.c
8 * Changed by HuTao Apr18, 2003
10 * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
11 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
12 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
14 * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
15 * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
16 * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
18 * Adapted for BlackFin BF537 by Bas Vermeulen <bas@buyways.nl>
19 * Copyright (c) 2003 BuyWays B.V. (www.buyways.nl)
21 * See file CREDITS for list of people who contributed to this
24 * This program is free software; you can redistribute it and/or
25 * modify it under the terms of the GNU General Public License as
26 * published by the Free Software Foundation; either version 2 of
27 * the License, or (at your option) any later version.
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
44 * Interrupt source definitions
45 * Event Source Core Event Name Number
51 * Hardware Error IVHW 5
53 * PLL Wakeup Interrupt IVG7 7
54 * DMA Error (generic) IVG7 8
55 * PPI Error Interrupt IVG7 9
56 * SPORT0 Error Interrupt IVG7 10
57 * SPORT1 Error Interrupt IVG7 11
58 * SPI Error Interrupt IVG7 12
59 * UART Error Interrupt IVG7 13
60 * RTC Interrupt IVG8 14
61 * DMA0 Interrupt (PPI) IVG8 15
62 * DMA1 (SPORT0 RX) IVG9 16
63 * DMA2 (SPORT0 TX) IVG9 17
64 * DMA3 (SPORT1 RX) IVG9 18
65 * DMA4 (SPORT1 TX) IVG9 19
67 * DMA6 (UART RX) IVG10 21
68 * DMA7 (UART TX) IVG10 22
72 * PF Interrupt A IVG12 26
73 * PF Interrupt B IVG12 27
74 * DMA8/9 Interrupt IVG13 28
75 * DMA10/11 Interrupt IVG13 29
76 * Watchdog Timer IVG13 30
77 * Software Interrupt 1 IVG14 31
78 * Software Interrupt 2 --
79 * (lowest priority) IVG15 32
82 #define IRQ_EMU 0 /* Emulation */
83 #define IRQ_RST 1 /* reset */
84 #define IRQ_NMI 2 /* Non Maskable */
85 #define IRQ_EVX 3 /* Exception */
86 #define IRQ_UNUSED 4 /* - unused interrupt */
87 #define IRQ_HWERR 5 /* Hardware Error */
88 #define IRQ_CORETMR 6 /* Core timer */
90 #define IRQ_UART_RX_BIT 0x0800
91 #define IRQ_UART_TX_BIT 0x1000
92 #define IRQ_UART_ERROR_BIT 0x40