3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_ARCH_MX31_REGS_H
25 #define __ASM_ARCH_MX31_REGS_H
27 #define __REG(x) (*((volatile u32 *)(x)))
28 #define __REG16(x) (*((volatile u16 *)(x)))
29 #define __REG8(x) (*((volatile u8 *)(x)))
31 #define CCM_BASE 0x53f80000
32 #define CCM_CCMR (CCM_BASE + 0x00)
33 #define CCM_PDR0 (CCM_BASE + 0x04)
34 #define CCM_PDR1 (CCM_BASE + 0x08)
35 #define CCM_RCSR (CCM_BASE + 0x0c)
36 #define CCM_MPCTL (CCM_BASE + 0x10)
37 #define CCM_UPCTL (CCM_BASE + 0x10)
38 #define CCM_SPCTL (CCM_BASE + 0x18)
39 #define CCM_COSR (CCM_BASE + 0x1C)
41 #define CCMR_MDS (1 << 7)
42 #define CCMR_SBYCS (1 << 4)
43 #define CCMR_MPE (1 << 3)
44 #define CCMR_PRCS_MASK (3 << 1)
45 #define CCMR_FPM (1 << 1)
46 #define CCMR_CKIH (2 << 1)
48 #define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
49 #define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
50 #define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
51 #define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
52 #define PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
53 #define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
54 #define PDR0_MCU_PODF(x) ((x) & 0x7)
56 #define PLL_PD(x) (((x) & 0xf) << 26)
57 #define PLL_MFD(x) (((x) & 0x3ff) << 16)
58 #define PLL_MFI(x) (((x) & 0xf) << 10)
59 #define PLL_MFN(x) (((x) & 0x3ff) << 0)
61 #define WEIM_BASE 0xb8002000
62 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10)
63 #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10)
64 #define CSCR_A(x) (WEIM_BASE + 8 + (x) * 0x10)
66 #define IOMUXC_BASE 0x43FAC000
67 #define IOMUXC_GPR (IOMUXC_BASE + 0x8)
68 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)
69 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)
71 #define IPU_BASE 0x53fc0000
72 #define IPU_CONF IPU_BASE
74 #define IPU_CONF_PXL_ENDIAN (1<<8)
75 #define IPU_CONF_DU_EN (1<<7)
76 #define IPU_CONF_DI_EN (1<<6)
77 #define IPU_CONF_ADC_EN (1<<5)
78 #define IPU_CONF_SDC_EN (1<<4)
79 #define IPU_CONF_PF_EN (1<<3)
80 #define IPU_CONF_ROT_EN (1<<2)
81 #define IPU_CONF_IC_EN (1<<1)
82 #define IPU_CONF_SCI_EN (1<<0)
84 #define WDOG_BASE 0x53FDC000
87 * Signal Multiplexing (IOMUX)
90 /* bits in the SW_MUX_CTL registers */
91 #define MUX_CTL_OUT_GPIO_DR (0 << 4)
92 #define MUX_CTL_OUT_FUNC (1 << 4)
93 #define MUX_CTL_OUT_ALT1 (2 << 4)
94 #define MUX_CTL_OUT_ALT2 (3 << 4)
95 #define MUX_CTL_OUT_ALT3 (4 << 4)
96 #define MUX_CTL_OUT_ALT4 (5 << 4)
97 #define MUX_CTL_OUT_ALT5 (6 << 4)
98 #define MUX_CTL_OUT_ALT6 (7 << 4)
99 #define MUX_CTL_IN_NONE (0 << 0)
100 #define MUX_CTL_IN_GPIO (1 << 0)
101 #define MUX_CTL_IN_FUNC (2 << 0)
102 #define MUX_CTL_IN_ALT1 (4 << 0)
103 #define MUX_CTL_IN_ALT2 (8 << 0)
105 #define MUX_CTL_FUNC (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
106 #define MUX_CTL_ALT1 (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
107 #define MUX_CTL_ALT2 (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
108 #define MUX_CTL_GPIO (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
110 /* Register offsets based on IOMUXC_BASE */
112 #define MUX_CTL_RTS1 0x7c
113 #define MUX_CTL_CTS1 0x7d
114 #define MUX_CTL_DTR_DCE1 0x7e
115 #define MUX_CTL_DSR_DCE1 0x7f
116 #define MUX_CTL_CSPI2_SCLK 0x80
117 #define MUX_CTL_CSPI2_SPI_RDY 0x81
118 #define MUX_CTL_RXD1 0x82
119 #define MUX_CTL_TXD1 0x83
120 #define MUX_CTL_CSPI2_MISO 0x84
122 #define MUX_CTL_CSPI2_MOSI 0x8b
124 /* The modes a specific pin can be in
125 * these macros can be used in mx31_gpio_mux() and have the form
126 * MUX_[contact name]__[pin function]
128 #define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
129 #define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
130 #define MUX_RTS1__UART1_RTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
131 #define MUX_RTS1__UART1_CTS_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
133 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
134 #define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
136 #endif /* __ASM_ARCH_MX31_REGS_H */