3 /* ------------------------------------------------------------------------
4 * Motorola IMX system registers
5 * ------------------------------------------------------------------------
10 # define __REG(x) (*((volatile u32 *)(x)))
11 # define __REG2(x,y) \
12 ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
13 : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
16 # define __REG2(x,y) ((x)+(y))
19 #define IMX_IO_BASE 0x00200000
22 * Register BASEs, based on OFFSETs
25 #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
26 #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
27 #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
28 #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
29 #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
30 #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
31 #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
32 #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
33 #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
34 #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
35 #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
36 #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
37 #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
38 #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
39 #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
40 #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
41 #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
42 #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
43 #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
44 #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
45 #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
46 #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
47 #define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
48 #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
49 #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
50 #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
51 #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
52 #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
53 #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
55 /* SYSCTRL Registers */
56 #define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
57 #define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
58 #define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
60 /* Chip Select Registers */
61 #define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
62 #define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
63 #define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
64 #define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
65 #define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
66 #define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
67 #define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
68 #define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
69 #define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
70 #define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
71 #define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
72 #define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
73 #define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
75 /* SDRAM controller registers */
77 #define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
78 #define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
79 #define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
80 #define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
83 #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
84 #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
85 #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
86 #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
87 #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
88 #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
90 #define CSCR_MPLL_RESTART (1<<21)
93 * GPIO Module and I/O Multiplexer
94 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
96 #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
97 #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
98 #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
99 #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
100 #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
101 #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
102 #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
103 #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
104 #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
105 #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
106 #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
107 #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
108 #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
109 #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
110 #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
111 #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
112 #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
114 #define GPIO_PIN_MASK 0x1f
115 #define GPIO_PORT_MASK (0x3 << 5)
117 #define GPIO_PORTA (0<<5)
118 #define GPIO_PORTB (1<<5)
119 #define GPIO_PORTC (2<<5)
120 #define GPIO_PORTD (3<<5)
122 #define GPIO_OUT (1<<7)
123 #define GPIO_IN (0<<7)
124 #define GPIO_PUEN (1<<8)
126 #define GPIO_PF (0<<9)
127 #define GPIO_AF (1<<9)
129 #define GPIO_OCR_MASK (3<<10)
130 #define GPIO_AIN (0<<10)
131 #define GPIO_BIN (1<<10)
132 #define GPIO_CIN (2<<10)
133 #define GPIO_GPIO (3<<10)
135 #define GPIO_AOUT (1<<12)
136 #define GPIO_BOUT (1<<13)
138 /* assignements for GPIO alternate/primary functions */
140 /* FIXME: This list is not completed. The correct directions are
141 * missing on some (many) pins
143 #define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
144 #define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
145 #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
146 #define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
147 #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
148 #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
149 #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
150 #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
151 #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
152 #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
153 #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
154 #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
155 #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
156 #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
157 #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
158 #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
159 #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
160 #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
161 #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
162 #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
163 #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
164 #define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
165 #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
166 #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
167 #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
168 #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
169 #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
170 #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
171 #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
172 #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
173 #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
174 #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
175 #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
176 #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
177 #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
178 #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
179 #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
180 #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
181 #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
182 #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
183 #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
184 #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
185 #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
186 #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
187 #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
188 #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
189 #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
190 #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
191 #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
192 #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
193 #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
194 #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
195 #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
196 #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
197 #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
198 #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
199 #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
200 #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
201 #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
202 #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
203 #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
204 #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
205 #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
206 #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
207 #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
208 #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
209 #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
210 #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
211 #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
212 #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
213 #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
214 #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
215 #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
216 #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
217 #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
218 #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
219 #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
220 #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
221 #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
222 #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
223 #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
224 #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
225 #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
226 #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
227 #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
228 #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
229 #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
230 #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
231 #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
232 #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
233 #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
234 #define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
235 #define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
236 #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
237 #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
238 #define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
239 #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
240 #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
241 #define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
242 #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
243 #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
244 #define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
245 #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
246 #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
247 #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
248 #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
249 #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
250 #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
251 #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
252 #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
253 #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
254 #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
255 #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
256 #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
257 #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
258 #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
259 #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
260 #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
261 #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
262 #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
263 #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
264 #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
265 #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
266 #define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
271 #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
272 #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
273 #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
274 #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
275 #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
276 #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
277 #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
278 #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
279 #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
280 #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
281 #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
282 #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
283 #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
284 #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
285 #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
286 #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
287 #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
288 #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /*Â Control Registers */
289 #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
290 #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
291 #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
292 #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
294 /* TODO: define DMA_REQ lines */
296 #define DCR_DRST (1<<1)
297 #define DCR_DEN (1<<0)
298 #define DBTOCR_EN (1<<15)
299 #define DBTOCR_CNT(x) ((x) & 0x7fff )
300 #define CNTR_CNT(x) ((x) & 0xffffff )
301 #define CCR_DMOD_LINEAR ( 0x0 << 12 )
302 #define CCR_DMOD_2D ( 0x1 << 12 )
303 #define CCR_DMOD_FIFO ( 0x2 << 12 )
304 #define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
305 #define CCR_SMOD_LINEAR ( 0x0 << 10 )
306 #define CCR_SMOD_2D ( 0x1 << 10 )
307 #define CCR_SMOD_FIFO ( 0x2 << 10 )
308 #define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
309 #define CCR_MDIR_DEC (1<<9)
310 #define CCR_MSEL_B (1<<8)
311 #define CCR_DSIZ_32 ( 0x0 << 6 )
312 #define CCR_DSIZ_8 ( 0x1 << 6 )
313 #define CCR_DSIZ_16 ( 0x2 << 6 )
314 #define CCR_SSIZ_32 ( 0x0 << 4 )
315 #define CCR_SSIZ_8 ( 0x1 << 4 )
316 #define CCR_SSIZ_16 ( 0x2 << 4 )
317 #define CCR_REN (1<<3)
318 #define CCR_RPT (1<<2)
319 #define CCR_FRC (1<<1)
320 #define CCR_CEN (1<<0)
321 #define RTOR_EN (1<<15)
322 #define RTOR_CLK (1<<14)
323 #define RTOR_PSC (1<<13)
329 #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
331 #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
332 #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
333 #define SIZE_YMAX(y) ( (y) & 0x1ff )
335 #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
336 #define VPW_VPW(x) ( (x) & 0x3ff )
338 #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
339 #define CPOS_CC1 (1<<31)
340 #define CPOS_CC0 (1<<30)
341 #define CPOS_OP (1<<28)
342 #define CPOS_CXP(x) (((x) & 3ff) << 16)
343 #define CPOS_CYP(y) ((y) & 0x1ff)
345 #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
346 #define LCWHB_BK_EN (1<<31)
347 #define LCWHB_CW(w) (((w) & 0x1f) << 24)
348 #define LCWHB_CH(h) (((h) & 0x1f) << 16)
349 #define LCWHB_BD(x) ((x) & 0xff)
351 #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
352 #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
353 #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
354 #define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
356 #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
357 #define PCR_TFT (1<<31)
358 #define PCR_COLOR (1<<30)
359 #define PCR_PBSIZ_1 (0<<28)
360 #define PCR_PBSIZ_2 (1<<28)
361 #define PCR_PBSIZ_4 (2<<28)
362 #define PCR_PBSIZ_8 (3<<28)
363 #define PCR_BPIX_1 (0<<25)
364 #define PCR_BPIX_2 (1<<25)
365 #define PCR_BPIX_4 (2<<25)
366 #define PCR_BPIX_8 (3<<25)
367 #define PCR_BPIX_12 (4<<25)
368 #define PCR_BPIX_16 (4<<25)
369 #define PCR_PIXPOL (1<<24)
370 #define PCR_FLMPOL (1<<23)
371 #define PCR_LPPOL (1<<22)
372 #define PCR_CLKPOL (1<<21)
373 #define PCR_OEPOL (1<<20)
374 #define PCR_SCLKIDLE (1<<19)
375 #define PCR_END_SEL (1<<18)
376 #define PCR_END_BYTE_SWAP (1<<17)
377 #define PCR_REV_VS (1<<16)
378 #define PCR_ACD_SEL (1<<15)
379 #define PCR_ACD(x) (((x) & 0x7f) << 8)
380 #define PCR_SCLK_SEL (1<<7)
381 #define PCR_SHARP (1<<6)
382 #define PCR_PCD(x) ((x) & 0x3f)
384 #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
385 #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
386 #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
387 #define HCR_H_WAIT_2(x) ((x) & 0xff)
389 #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
390 #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
391 #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
392 #define VCR_V_WAIT_2(x) ((x) & 0xff)
394 #define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
395 #define POS_POS(x) ((x) & 1f)
397 #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
398 #define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
399 #define LSCR1_GRAY2(x) ((x) & 0xf)
401 #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
402 #define PWMR_CLS(x) (((x) & 0x1ff) << 16)
403 #define PWMR_LDMSK (1<<15)
404 #define PWMR_SCR1 (1<<10)
405 #define PWMR_SCR0 (1<<9)
406 #define PWMR_CC_EN (1<<8)
407 #define PWMR_PW(x) ((x) & 0xff)
409 #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
410 #define DMACR_BURST (1<<31)
411 #define DMACR_HM(x) (((x) & 0xf) << 16)
412 #define DMACR_TM(x) ((x) &0xf)
414 #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
415 #define RMCR_LCDC_EN (1<<1)
416 #define RMCR_SELF_REF (1<<0)
418 #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
419 #define LCDICR_INT_SYN (1<<2)
420 #define LCDICR_INT_CON (1)
422 #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
423 #define LCDISR_UDR_ERR (1<<3)
424 #define LCDISR_ERR_RES (1<<2)
425 #define LCDISR_EOF (1<<1)
426 #define LCDISR_BOF (1<<0)
430 #define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */
431 #define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */
432 #define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */
433 #define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */
434 #define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */
435 #define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */
436 #define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */
437 #define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */
438 #define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */
439 #define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */
440 #define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */
441 #define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */
442 #define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */
443 #define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */
444 #define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */
445 #define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */
446 #define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */
447 #define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */
448 #define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */
449 #define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */
450 #define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */
451 #define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */
452 #define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */
454 /* UART Control Register Bit Fields.*/
455 #define URXD_CHARRDY (1<<15)
456 #define URXD_ERR (1<<14)
457 #define URXD_OVRRUN (1<<13)
458 #define URXD_FRMERR (1<<12)
459 #define URXD_BRK (1<<11)
460 #define URXD_PRERR (1<<10)
461 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
462 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
463 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
464 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
465 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
466 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
467 #define UCR1_IREN (1<<7) /* Infrared interface enable */
468 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
469 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
470 #define UCR1_SNDBRK (1<<4) /* Send break */
471 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
472 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
473 #define UCR1_DOZE (1<<1) /* Doze */
474 #define UCR1_UARTEN (1<<0) /* UART enabled */
475 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
476 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
477 #define UCR2_CTSC (1<<13) /* CTS pin control */
478 #define UCR2_CTS (1<<12) /* Clear to send */
479 #define UCR2_ESCEN (1<<11) /* Escape enable */
480 #define UCR2_PREN (1<<8) /* Parity enable */
481 #define UCR2_PROE (1<<7) /* Parity odd/even */
482 #define UCR2_STPB (1<<6) /* Stop */
483 #define UCR2_WS (1<<5) /* Word size */
484 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
485 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
486 #define UCR2_RXEN (1<<1) /* Receiver enabled */
487 #define UCR2_SRST (1<<0) /* SW reset */
488 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
489 #define UCR3_PARERREN (1<<12) /* Parity enable */
490 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
491 #define UCR3_DSR (1<<10) /* Data set ready */
492 #define UCR3_DCD (1<<9) /* Data carrier detect */
493 #define UCR3_RI (1<<8) /* Ring indicator */
494 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
495 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
496 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
497 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
498 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
499 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
500 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
501 #define UCR3_BPEN (1<<0) /* Preset registers enable */
502 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
503 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
504 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
505 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
506 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
507 #define UCR4_IRSC (1<<5) /* IR special case */
508 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
509 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
510 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
511 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
512 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
513 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
514 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
515 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
516 #define USR1_RTSS (1<<14) /* RTS pin status */
517 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
518 #define USR1_RTSD (1<<12) /* RTS delta */
519 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
520 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
521 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
522 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
523 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
524 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
525 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
526 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
527 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
528 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
529 #define USR2_IDLE (1<<12) /* Idle condition */
530 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
531 #define USR2_WAKE (1<<7) /* Wake */
532 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
533 #define USR2_TXDC (1<<3) /* Transmitter complete */
534 #define USR2_BRCD (1<<2) /* Break condition */
535 #define USR2_ORE (1<<1) /* Overrun error */
536 #define USR2_RDR (1<<0) /* Recv data ready */
537 #define UTS_FRCPERR (1<<13) /* Force parity error */
538 #define UTS_LOOP (1<<12) /* Loop tx and rx */
539 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
540 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
541 #define UTS_TXFULL (1<<4) /* TxFIFO full */
542 #define UTS_RXFULL (1<<3) /* RxFIFO full */
543 #define UTS_SOFTRST (1<<0) /* Software reset */
545 /* General purpose timers registers */
546 #define TCTL1 __REG(IMX_TIM1_BASE)
547 #define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
548 #define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
549 #define TCR1 __REG(IMX_TIM1_BASE + 0xc)
550 #define TCN1 __REG(IMX_TIM1_BASE + 0x10)
551 #define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
552 #define TCTL2 __REG(IMX_TIM2_BASE)
553 #define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
554 #define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
555 #define TCR2 __REG(IMX_TIM2_BASE + 0xc)
556 #define TCN2 __REG(IMX_TIM2_BASE + 0x10)
557 #define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
559 /* General purpose timers bitfields */
560 #define TCTL_SWR (1<<15) /* Software reset */
561 #define TCTL_FRR (1<<8) /* Freerun / restart */
562 #define TCTL_CAP (3<<6) /* Capture Edge */
563 #define TCTL_OM (1<<5) /* output mode */
564 #define TCTL_IRQEN (1<<4) /* interrupt enable */
565 #define TCTL_CLKSOURCE (7<<1) /* Clock source */
566 #define TCTL_TEN (1) /* Timer enable */
567 #define TPRER_PRES (0xff) /* Prescale */
568 #define TSTAT_CAPT (1<<1) /* Capture event */
569 #define TSTAT_COMP (1) /* Compare event */
571 #endif /* _IMX_REGS_H */