2 * Cirrus Logic EP93xx register definitions.
5 * Matthias Kaehlcke <matthias@kaehlcke.net>
8 * Dominic Rath <Dominic.Rath@gmx.de>
10 * Copyright (C) 2004, 2005
11 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
13 * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
15 * Copyright (C) 2004 Ray Lehtiniemi
16 * Copyright (C) 2003 Cirrus Logic, Inc
17 * Copyright (C) 1999 ARM Limited.
19 * See file CREDITS for list of people who contributed to this project.
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation; either version 2 of the License, or
24 * (at your option) any later version.
26 * This program is distributed in the hope that it will be useful, but
27 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
28 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 #define EP93XX_AHB_BASE 0x80000000
37 #define EP93XX_APB_BASE 0x80800000
40 * 0x80000000 - 0x8000FFFF: DMA
42 #define DMA_OFFSET 0x000000
43 #define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
53 uint32_t reserved1[2];
65 struct dma_channel m2p_channel_0;
66 struct dma_channel m2p_channel_1;
67 struct dma_channel m2p_channel_2;
68 struct dma_channel m2p_channel_3;
69 struct dma_channel m2m_channel_0;
70 struct dma_channel m2m_channel_1;
71 struct dma_channel reserved0[2];
72 struct dma_channel m2p_channel_5;
73 struct dma_channel m2p_channel_4;
74 struct dma_channel m2p_channel_7;
75 struct dma_channel m2p_channel_6;
76 struct dma_channel m2p_channel_9;
77 struct dma_channel m2p_channel_8;
78 uint32_t channel_arbitration;
79 uint32_t reserved[15];
80 uint32_t global_interrupt;
85 * 0x80010000 - 0x8001FFFF: Ethernet MAC
87 #define MAC_OFFSET 0x010000
88 #define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
93 union { /* deal with half-word aligned registers */
116 uint32_t reserved2[2];
126 uint32_t indad_upper;
130 uint32_t reserved3[2];
143 struct mac_queue rxdq;
145 struct mac_queue rxstsq;
147 struct mac_queue txdq;
149 struct mac_queue txstsq;
151 uint32_t rxbufthrshld;
152 uint32_t txbufthrshld;
153 uint32_t rxststhrshld;
154 uint32_t txststhrshld;
162 #define SELFCTL_RWP (1 << 7)
163 #define SELFCTL_GPO0 (1 << 5)
164 #define SELFCTL_PUWE (1 << 4)
165 #define SELFCTL_PDWE (1 << 3)
166 #define SELFCTL_MIIL (1 << 2)
167 #define SELFCTL_RESET (1 << 0)
169 #define INTSTS_RWI (1 << 30)
170 #define INTSTS_RXMI (1 << 29)
171 #define INTSTS_RXBI (1 << 28)
172 #define INTSTS_RXSQI (1 << 27)
173 #define INTSTS_TXLEI (1 << 26)
174 #define INTSTS_ECIE (1 << 25)
175 #define INTSTS_TXUHI (1 << 24)
176 #define INTSTS_MOI (1 << 18)
177 #define INTSTS_TXCOI (1 << 17)
178 #define INTSTS_RXROI (1 << 16)
179 #define INTSTS_MIII (1 << 12)
180 #define INTSTS_PHYI (1 << 11)
181 #define INTSTS_TI (1 << 10)
182 #define INTSTS_AHBE (1 << 8)
183 #define INTSTS_OTHER (1 << 4)
184 #define INTSTS_TXSQ (1 << 3)
185 #define INTSTS_RXSQ (1 << 2)
187 #define BMCTL_MT (1 << 13)
188 #define BMCTL_TT (1 << 12)
189 #define BMCTL_UNH (1 << 11)
190 #define BMCTL_TXCHR (1 << 10)
191 #define BMCTL_TXDIS (1 << 9)
192 #define BMCTL_TXEN (1 << 8)
193 #define BMCTL_EH2 (1 << 6)
194 #define BMCTL_EH1 (1 << 5)
195 #define BMCTL_EEOB (1 << 4)
196 #define BMCTL_RXCHR (1 << 2)
197 #define BMCTL_RXDIS (1 << 1)
198 #define BMCTL_RXEN (1 << 0)
200 #define BMSTS_TXACT (1 << 7)
201 #define BMSTS_TP (1 << 4)
202 #define BMSTS_RXACT (1 << 3)
203 #define BMSTS_QID_MASK 0x07
204 #define BMSTS_QID_RXDATA 0x00
205 #define BMSTS_QID_TXDATA 0x01
206 #define BMSTS_QID_RXSTS 0x02
207 #define BMSTS_QID_TXSTS 0x03
208 #define BMSTS_QID_RXDESC 0x04
209 #define BMSTS_QID_TXDESC 0x05
211 #define AFP_MASK 0x07
212 #define AFP_IAPRIMARY 0x00
213 #define AFP_IASECONDARY1 0x01
214 #define AFP_IASECONDARY2 0x02
215 #define AFP_IASECONDARY3 0x03
217 #define AFP_HASH 0x07
219 #define RXCTL_PAUSEA (1 << 20)
220 #define RXCTL_RXFCE1 (1 << 19)
221 #define RXCTL_RXFCE0 (1 << 18)
222 #define RXCTL_BCRC (1 << 17)
223 #define RXCTL_SRXON (1 << 16)
224 #define RXCTL_RCRCA (1 << 13)
225 #define RXCTL_RA (1 << 12)
226 #define RXCTL_PA (1 << 11)
227 #define RXCTL_BA (1 << 10)
228 #define RXCTL_MA (1 << 9)
229 #define RXCTL_IAHA (1 << 8)
230 #define RXCTL_IA3 (1 << 3)
231 #define RXCTL_IA2 (1 << 2)
232 #define RXCTL_IA1 (1 << 1)
233 #define RXCTL_IA0 (1 << 0)
235 #define TXCTL_DEFDIS (1 << 7)
236 #define TXCTL_MBE (1 << 6)
237 #define TXCTL_ICRC (1 << 5)
238 #define TXCTL_TPD (1 << 4)
239 #define TXCTL_OCOLL (1 << 3)
240 #define TXCTL_SP (1 << 2)
241 #define TXCTL_PB (1 << 1)
242 #define TXCTL_STXON (1 << 0)
244 #define MIICMD_REGAD_MASK (0x001F)
245 #define MIICMD_PHYAD_MASK (0x03E0)
246 #define MIICMD_OPCODE_MASK (0xC000)
247 #define MIICMD_PHYAD_8950 (0x0000)
248 #define MIICMD_OPCODE_READ (0x8000)
249 #define MIICMD_OPCODE_WRITE (0x4000)
251 #define MIISTS_BUSY (1 << 0)
254 * 0x80020000 - 0x8002FFFF: USB OHCI
256 #define USB_OFFSET 0x020000
257 #define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
260 * 0x80030000 - 0x8003FFFF: Raster engine
262 #if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
263 #define RASTER_OFFSET 0x030000
264 #define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
268 * 0x80040000 - 0x8004FFFF: Graphics accelerator
270 #if defined(CONFIG_EP9315)
271 #define GFX_OFFSET 0x040000
272 #define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
276 * 0x80050000 - 0x8005FFFF: Reserved
280 * 0x80060000 - 0x8006FFFF: SDRAM controller
282 #define SDRAM_OFFSET 0x060000
283 #define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
298 #define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
299 #define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
300 #define SDRAM_DEVCFG_SROMLL (1 << 5)
301 #define SDRAM_DEVCFG_CASLAT_2 0x00010000
302 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
304 #define GLCONFIG_INIT (1 << 0)
305 #define GLCONFIG_MRS (1 << 1)
306 #define GLCONFIG_SMEMBUSY (1 << 5)
307 #define GLCONFIG_LCR (1 << 6)
308 #define GLCONFIG_REARBEN (1 << 7)
309 #define GLCONFIG_CLKSHUTDOWN (1 << 30)
310 #define GLCONFIG_CKE (1 << 31)
313 * 0x80070000 - 0x8007FFFF: Reserved
317 * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
319 #define SMC_OFFSET 0x080000
320 #define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
328 uint32_t reserved0[2];
331 #if defined(CONFIG_EP9315)
332 uint32_t pcattribute;
335 uint32_t reserved1[5];
341 #define SMC_BCR_IDCY_SHIFT 0
342 #define SMC_BCR_WST1_SHIFT 5
343 #define SMC_BCR_BLE (1 << 10)
344 #define SMC_BCR_WST2_SHIFT 11
345 #define SMC_BCR_MW_SHIFT 28
348 * 0x80090000 - 0x8009FFFF: Boot ROM
352 * 0x800A0000 - 0x800AFFFF: IDE interface
356 * 0x800B0000 - 0x800BFFFF: VIC1
360 * 0x800C0000 - 0x800CFFFF: VIC2
364 * 0x800D0000 - 0x800FFFFF: Reserved
368 * 0x80800000 - 0x8080FFFF: Reserved
372 * 0x80810000 - 0x8081FFFF: Timers
374 #define TIMER_OFFSET 0x010000
375 #define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
392 uint32_t reserved0[4];
394 uint32_t reserved1[12];
395 struct timer4 timer4;
396 uint32_t reserved2[6];
402 * 0x80820000 - 0x8082FFFF: I2S
404 #define I2S_OFFSET 0x020000
405 #define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
408 * 0x80830000 - 0x8083FFFF: Security
410 #define SECURITY_OFFSET 0x030000
411 #define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
413 #define EXTENSIONID (SECURITY_BASE + 0x2714)
416 * 0x80840000 - 0x8084FFFF: GPIO
418 #define GPIO_OFFSET 0x040000
419 #define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
443 uint32_t reserved0[2];
454 struct gpio_int pfint;
455 uint32_t reserved3[10];
456 struct gpio_int paint;
457 struct gpio_int pbint;
463 * 0x80850000 - 0x8087FFFF: Reserved
467 * 0x80880000 - 0x8088FFFF: AAC
469 #define AAC_OFFSET 0x080000
470 #define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
473 * 0x80890000 - 0x8089FFFF: Reserved
477 * 0x808A0000 - 0x808AFFFF: SPI
479 #define SPI_OFFSET 0x0A0000
480 #define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
483 * 0x808B0000 - 0x808BFFFF: IrDA
485 #define IRDA_OFFSET 0x0B0000
486 #define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
489 * 0x808C0000 - 0x808CFFFF: UART1
491 #define UART1_OFFSET 0x0C0000
492 #define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
495 * 0x808D0000 - 0x808DFFFF: UART2
497 #define UART2_OFFSET 0x0D0000
498 #define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
501 * 0x808E0000 - 0x808EFFFF: UART3
503 #define UART3_OFFSET 0x0E0000
504 #define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
507 * 0x808F0000 - 0x808FFFFF: Key Matrix
509 #define KEY_OFFSET 0x0F0000
510 #define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
513 * 0x80900000 - 0x8090FFFF: Touchscreen
515 #define TOUCH_OFFSET 0x900000
516 #define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
519 * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
521 #define PWM_OFFSET 0x910000
522 #define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
525 * 0x80920000 - 0x8092FFFF: Real time clock
527 #define RTC_OFFSET 0x920000
528 #define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
531 * 0x80930000 - 0x8093FFFF: Syscon
533 #define SYSCON_OFFSET 0x930000
534 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
542 uint32_t reserved0[2];
547 uint32_t reserved1[6];
550 uint32_t reserved2[2];
552 uint32_t bustmstrarb;
553 uint32_t bootmodeclr;
554 uint32_t reserved3[9];
559 uint32_t keytchclkdiv;
562 uint32_t reserved4[8];
566 #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
569 #define SYSCON_PWRCNT_UART_BAUD (1 << 29)
571 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
572 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
573 #define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
574 #define SYSCON_CLKSET_PLL_PS_SHIFT 16
575 #define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
576 #define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
577 #define SYSCON_CLKSET1_NBYP1 (1 << 23)
578 #define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
580 #define SYSCON_CLKSET2_PLL2_EN (1 << 18)
581 #define SYSCON_CLKSET2_NBYP2 (1 << 19)
582 #define SYSCON_CLKSET2_USB_DIV_SHIFT 28
584 #define SYSCON_CHIPID_REV_MASK 0xF0000000
585 #define SYSCON_DEVICECFG_SWRST (1 << 31)
588 * 0x80930000 - 0x8093FFFF: Watchdog Timer
590 #define WATCHDOG_OFFSET 0x940000
591 #define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
594 * 0x80950000 - 0x9000FFFF: Reserved