1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
21 /*----------------------------------------------------------------------------+
23 | File Name: enetemac.h
25 | Function: Header file for the EMAC3 macro on the 405GP.
31 | Date Description of Change BY
32 | --------- --------------------- ---
33 | 29-Apr-99 Created MKW
35 +----------------------------------------------------------------------------*/
40 /*-----------------------------------------------------------------------------+
41 | General enternet defines. 802 frames are not supported.
42 +-----------------------------------------------------------------------------*/
43 #define ENET_ADDR_LENGTH 6
44 #define ENET_ARPTYPE 0x806
47 #define ENET_IPTYPE 0x800
48 #define ARP_CACHE_SIZE 5
52 unsigned char dest_addr[ENET_ADDR_LENGTH];
53 unsigned char source_addr[ENET_ADDR_LENGTH];
55 unsigned char enet_data[1];
59 unsigned long inet_address;
60 unsigned char mac_address[ENET_ADDR_LENGTH];
67 /*Register addresses */
68 #if defined(CONFIG_440)
69 #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
70 #define ZMII_FER (ZMII_BASE)
71 #define ZMII_SSR (ZMII_BASE + 4)
72 #define ZMII_SMIISR (ZMII_BASE + 8)
74 #define ZMII_RMII 0x22000000
75 #define ZMII_MDI0 0x80000000
76 #endif /* CONFIG_440 */
78 #if defined(CONFIG_440)
79 #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
81 #define EMAC_BASE 0xEF600800
84 #define EMAC_M0 (EMAC_BASE)
85 #define EMAC_M1 (EMAC_BASE + 4)
86 #define EMAC_TXM0 (EMAC_BASE + 8)
87 #define EMAC_TXM1 (EMAC_BASE + 12)
88 #define EMAC_RXM (EMAC_BASE + 16)
89 #define EMAC_ISR (EMAC_BASE + 20)
90 #define EMAC_IER (EMAC_BASE + 24)
91 #define EMAC_IAH (EMAC_BASE + 28)
92 #define EMAC_IAL (EMAC_BASE + 32)
93 #define EMAC_VLAN_TPID_REG (EMAC_BASE + 36)
94 #define EMAC_VLAN_TCI_REG (EMAC_BASE + 40)
95 #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
96 #define EMAC_IND_HASH_1 (EMAC_BASE + 48)
97 #define EMAC_IND_HASH_2 (EMAC_BASE + 52)
98 #define EMAC_IND_HASH_3 (EMAC_BASE + 56)
99 #define EMAC_IND_HASH_4 (EMAC_BASE + 60)
100 #define EMAC_GRP_HASH_1 (EMAC_BASE + 64)
101 #define EMAC_GRP_HASH_2 (EMAC_BASE + 68)
102 #define EMAC_GRP_HASH_3 (EMAC_BASE + 72)
103 #define EMAC_GRP_HASH_4 (EMAC_BASE + 76)
104 #define EMAC_LST_SRC_LOW (EMAC_BASE + 80)
105 #define EMAC_LST_SRC_HI (EMAC_BASE + 84)
106 #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
107 #define EMAC_STACR (EMAC_BASE + 92)
108 #define EMAC_TRTR (EMAC_BASE + 96)
109 #define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
111 /* bit definitions */
113 #define EMAC_M0_RXI 0x80000000
114 #define EMAC_M0_TXI 0x40000000
115 #define EMAC_M0_SRST 0x20000000
116 #define EMAC_M0_TXE 0x10000000
117 #define EMAC_M0_RXE 0x08000000
118 #define EMAC_M0_WKE 0x04000000
121 #define EMAC_M1_FDE 0x80000000
122 #define EMAC_M1_ILE 0x40000000
123 #define EMAC_M1_VLE 0x20000000
124 #define EMAC_M1_EIFC 0x10000000
125 #define EMAC_M1_APP 0x08000000
126 #define EMAC_M1_AEMI 0x02000000
127 #define EMAC_M1_IST 0x01000000
128 #define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
129 #define EMAC_M1_MF_100MBPS 0x00400000
130 #define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */
131 #define EMAC_M1_RFS_2K 0x00200000
132 #define EMAC_M1_RFS_1K 0x00100000
133 #define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */
134 #define EMAC_M1_TX_FIFO_1K 0x00040000
135 #define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
136 #define EMAC_M1_TR0_MULTI 0x00008000
137 #define EMAC_M1_TR1_DEPEND 0x00004000
138 #define EMAC_M1_TR1_MULTI 0x00002000
139 #define EMAC_M1_JUMBO_ENABLE 0x00001000
141 /* Transmit Mode Register 0 */
142 #define EMAC_TXM0_GNP0 0x80000000
143 #define EMAC_TXM0_GNP1 0x40000000
144 #define EMAC_TXM0_GNPD 0x20000000
145 #define EMAC_TXM0_FC 0x10000000
147 /* Receive Mode Register */
148 #define EMAC_RMR_SP 0x80000000
149 #define EMAC_RMR_SFCS 0x40000000
150 #define EMAC_RMR_ARRP 0x20000000
151 #define EMAC_RMR_ARP 0x10000000
152 #define EMAC_RMR_AROP 0x08000000
153 #define EMAC_RMR_ARPI 0x04000000
154 #define EMAC_RMR_PPP 0x02000000
155 #define EMAC_RMR_PME 0x01000000
156 #define EMAC_RMR_PMME 0x00800000
157 #define EMAC_RMR_IAE 0x00400000
158 #define EMAC_RMR_MIAE 0x00200000
159 #define EMAC_RMR_BAE 0x00100000
160 #define EMAC_RMR_MAE 0x00080000
162 /* Interrupt Status & enable Regs */
163 #define EMAC_ISR_OVR 0x02000000
164 #define EMAC_ISR_PP 0x01000000
165 #define EMAC_ISR_BP 0x00800000
166 #define EMAC_ISR_RP 0x00400000
167 #define EMAC_ISR_SE 0x00200000
168 #define EMAC_ISR_SYE 0x00100000
169 #define EMAC_ISR_BFCS 0x00080000
170 #define EMAC_ISR_PTLE 0x00040000
171 #define EMAC_ISR_ORE 0x00020000
172 #define EMAC_ISR_IRE 0x00010000
173 #define EMAC_ISR_DBDM 0x00000200
174 #define EMAC_ISR_DB0 0x00000100
175 #define EMAC_ISR_SE0 0x00000080
176 #define EMAC_ISR_TE0 0x00000040
177 #define EMAC_ISR_DB1 0x00000020
178 #define EMAC_ISR_SE1 0x00000010
179 #define EMAC_ISR_TE1 0x00000008
180 #define EMAC_ISR_MOS 0x00000002
181 #define EMAC_ISR_MOF 0x00000001
184 /* STA CONTROL REG */
185 #define EMAC_STACR_OC 0x00008000
186 #define EMAC_STACR_PHYE 0x00004000
187 #define EMAC_STACR_WRITE 0x00002000
188 #define EMAC_STACR_READ 0x00001000
189 #define EMAC_STACR_CLK_83MHZ 0x00000800 /* 0's for 50Mhz */
190 #define EMAC_STACR_CLK_66MHZ 0x00000400
191 #define EMAC_STACR_CLK_100MHZ 0x00000C00
193 /* Transmit Request Threshold Register */
194 #define EMAC_TRTR_256 0x18000000 /* 0's for 64 Bytes */
195 #define EMAC_TRTR_192 0x10000000
196 #define EMAC_TRTR_128 0x01000000
198 /* the follwing defines are for the MadMAL status and control registers. */
199 /* For bits 0..5 look at the mal.h file */
200 #define EMAC_TX_CTRL_GFCS 0x0200
201 #define EMAC_TX_CTRL_GP 0x0100
202 #define EMAC_TX_CTRL_ISA 0x0080
203 #define EMAC_TX_CTRL_RSA 0x0040
204 #define EMAC_TX_CTRL_IVT 0x0020
205 #define EMAC_TX_CTRL_RVT 0x0010
207 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
209 #define EMAC_TX_ST_BFCS 0x0200
210 #define EMAC_TX_ST_BPP 0x0100
211 #define EMAC_TX_ST_LCS 0x0080
212 #define EMAC_TX_ST_ED 0x0040
213 #define EMAC_TX_ST_EC 0x0020
214 #define EMAC_TX_ST_LC 0x0010
215 #define EMAC_TX_ST_MC 0x0008
216 #define EMAC_TX_ST_SC 0x0004
217 #define EMAC_TX_ST_UR 0x0002
218 #define EMAC_TX_ST_SQE 0x0001
220 #define EMAC_TX_ST_DEFAULT 0x03F3
223 /* madmal receive status / Control bits */
225 #define EMAC_RX_ST_OE 0x0200
226 #define EMAC_RX_ST_PP 0x0100
227 #define EMAC_RX_ST_BP 0x0080
228 #define EMAC_RX_ST_RP 0x0040
229 #define EMAC_RX_ST_SE 0x0020
230 #define EMAC_RX_ST_AE 0x0010
231 #define EMAC_RX_ST_BFCS 0x0008
232 #define EMAC_RX_ST_PTL 0x0004
233 #define EMAC_RX_ST_ORE 0x0002
234 #define EMAC_RX_ST_IRE 0x0001
235 /* all the errors we care about */
236 #define EMAC_RX_ERRORS 0x03FF
239 /*-----------------------------------------------------------------------------+
240 | Function prototypes for device table.
241 +-----------------------------------------------------------------------------*/
242 #endif /* _enetLib_h_ */