2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * Register definitions for Freescale QSPI
6 * SPDX-License-Identifier: GPL-2.0+
12 struct fsl_qspi_regs {
56 #define QSPI_IPCR_SEQID_SHIFT 24
57 #define QSPI_IPCR_SEQID_MASK (0xf << QSPI_IPCR_SEQID_SHIFT)
59 #define QSPI_MCR_END_CFD_SHIFT 2
60 #define QSPI_MCR_END_CFD_MASK (3 << QSPI_MCR_END_CFD_SHIFT)
61 #ifdef CONFIG_SYS_FSL_QSPI_AHB
62 /* AHB needs 64bit operation */
63 #define QSPI_MCR_END_CFD_LE (3 << QSPI_MCR_END_CFD_SHIFT)
65 #define QSPI_MCR_END_CFD_LE (1 << QSPI_MCR_END_CFD_SHIFT)
67 #define QSPI_MCR_DDR_EN_SHIFT 7
68 #define QSPI_MCR_DDR_EN_MASK (1 << QSPI_MCR_DDR_EN_SHIFT)
69 #define QSPI_MCR_CLR_RXF_SHIFT 10
70 #define QSPI_MCR_CLR_RXF_MASK (1 << QSPI_MCR_CLR_RXF_SHIFT)
71 #define QSPI_MCR_CLR_TXF_SHIFT 11
72 #define QSPI_MCR_CLR_TXF_MASK (1 << QSPI_MCR_CLR_TXF_SHIFT)
73 #define QSPI_MCR_MDIS_SHIFT 14
74 #define QSPI_MCR_MDIS_MASK (1 << QSPI_MCR_MDIS_SHIFT)
75 #define QSPI_MCR_RESERVED_SHIFT 16
76 #define QSPI_MCR_RESERVED_MASK (0xf << QSPI_MCR_RESERVED_SHIFT)
77 #define QSPI_MCR_SWRSTHD_SHIFT 1
78 #define QSPI_MCR_SWRSTHD_MASK (1 << QSPI_MCR_SWRSTHD_SHIFT)
79 #define QSPI_MCR_SWRSTSD_SHIFT 0
80 #define QSPI_MCR_SWRSTSD_MASK (1 << QSPI_MCR_SWRSTSD_SHIFT)
82 #define QSPI_SMPR_HSENA_SHIFT 0
83 #define QSPI_SMPR_HSENA_MASK (1 << QSPI_SMPR_HSENA_SHIFT)
84 #define QSPI_SMPR_FSPHS_SHIFT 5
85 #define QSPI_SMPR_FSPHS_MASK (1 << QSPI_SMPR_FSPHS_SHIFT)
86 #define QSPI_SMPR_FSDLY_SHIFT 6
87 #define QSPI_SMPR_FSDLY_MASK (1 << QSPI_SMPR_FSDLY_SHIFT)
88 #define QSPI_SMPR_DDRSMP_SHIFT 16
89 #define QSPI_SMPR_DDRSMP_MASK (7 << QSPI_SMPR_DDRSMP_SHIFT)
91 #define QSPI_BUFXCR_INVALID_MSTRID 0xe
92 #define QSPI_BUF3CR_ALLMST_SHIFT 31
93 #define QSPI_BUF3CR_ALLMST_MASK (1 << QSPI_BUF3CR_ALLMST_SHIFT)
94 #define QSPI_BUF3CR_ADATSZ_SHIFT 8
95 #define QSPI_BUF3CR_ADATSZ_MASK (0xFF << QSPI_BUF3CR_ADATSZ_SHIFT)
97 #define QSPI_BFGENCR_SEQID_SHIFT 12
98 #define QSPI_BFGENCR_SEQID_MASK (0xf << QSPI_BFGENCR_SEQID_SHIFT)
99 #define QSPI_BFGENCR_PAR_EN_SHIFT 16
100 #define QSPI_BFGENCR_PAR_EN_MASK (1 << QSPI_BFGENCR_PAR_EN_SHIFT)
102 #define QSPI_RBSR_RDBFL_SHIFT 8
103 #define QSPI_RBSR_RDBFL_MASK (0x3f << QSPI_RBSR_RDBFL_SHIFT)
105 #define QSPI_RBCT_RXBRD_SHIFT 8
106 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
108 #define QSPI_SR_AHB_ACC_SHIFT 2
109 #define QSPI_SR_AHB_ACC_MASK (1 << QSPI_SR_AHB_ACC_SHIFT)
110 #define QSPI_SR_IP_ACC_SHIFT 1
111 #define QSPI_SR_IP_ACC_MASK (1 << QSPI_SR_IP_ACC_SHIFT)
112 #define QSPI_SR_BUSY_SHIFT 0
113 #define QSPI_SR_BUSY_MASK (1 << QSPI_SR_BUSY_SHIFT)
115 #define QSPI_LCKCR_LOCK 0x1
116 #define QSPI_LCKCR_UNLOCK 0x2
118 #define LUT_KEY_VALUE 0x5af05af0
120 #define OPRND0_SHIFT 0
121 #define OPRND0(x) ((x) << OPRND0_SHIFT)
123 #define PAD0(x) ((x) << PAD0_SHIFT)
124 #define INSTR0_SHIFT 10
125 #define INSTR0(x) ((x) << INSTR0_SHIFT)
126 #define OPRND1_SHIFT 16
127 #define OPRND1(x) ((x) << OPRND1_SHIFT)
128 #define PAD1_SHIFT 24
129 #define PAD1(x) ((x) << PAD1_SHIFT)
130 #define INSTR1_SHIFT 26
131 #define INSTR1(x) ((x) << INSTR1_SHIFT)
143 #define ADDR24BIT 0x18
144 #define ADDR32BIT 0x20
146 #endif /* _FSL_QSPI_H_ */