2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t *popts,
23 unsigned int ctrl_num);
26 unsigned int odt_rd_cfg;
27 unsigned int odt_wr_cfg;
28 unsigned int odt_rtt_norm;
29 unsigned int odt_rtt_wr;
32 #ifdef CONFIG_SYS_FSL_DDR4
33 /* Quad rank is not verified yet due availability.
34 * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
36 static const struct dynamic_odt single_Q[4] = {
39 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
40 DDR4_RTT_34_OHM, /* unverified */
51 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
57 FSL_DDR_ODT_NEVER, /* tied high */
63 static const struct dynamic_odt single_D[4] = {
80 static const struct dynamic_odt single_S[4] = {
92 static const struct dynamic_odt dual_DD[4] = {
95 FSL_DDR_ODT_SAME_DIMM,
100 FSL_DDR_ODT_OTHER_DIMM,
101 FSL_DDR_ODT_OTHER_DIMM,
107 FSL_DDR_ODT_SAME_DIMM,
112 FSL_DDR_ODT_OTHER_DIMM,
113 FSL_DDR_ODT_OTHER_DIMM,
119 static const struct dynamic_odt dual_DS[4] = {
122 FSL_DDR_ODT_SAME_DIMM,
127 FSL_DDR_ODT_OTHER_DIMM,
128 FSL_DDR_ODT_OTHER_DIMM,
133 FSL_DDR_ODT_OTHER_DIMM,
140 static const struct dynamic_odt dual_SD[4] = {
142 FSL_DDR_ODT_OTHER_DIMM,
150 FSL_DDR_ODT_SAME_DIMM,
155 FSL_DDR_ODT_OTHER_DIMM,
156 FSL_DDR_ODT_OTHER_DIMM,
162 static const struct dynamic_odt dual_SS[4] = {
164 FSL_DDR_ODT_OTHER_DIMM,
171 FSL_DDR_ODT_OTHER_DIMM,
179 static const struct dynamic_odt dual_D0[4] = {
182 FSL_DDR_ODT_SAME_DIMM,
196 static const struct dynamic_odt dual_0D[4] = {
201 FSL_DDR_ODT_SAME_DIMM,
213 static const struct dynamic_odt dual_S0[4] = {
226 static const struct dynamic_odt dual_0S[4] = {
239 static const struct dynamic_odt odt_unknown[4] = {
265 #elif defined(CONFIG_SYS_FSL_DDR3)
266 static const struct dynamic_odt single_Q[4] = {
269 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
275 FSL_DDR_ODT_NEVER, /* tied high */
281 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
287 FSL_DDR_ODT_NEVER, /* tied high */
293 static const struct dynamic_odt single_D[4] = {
310 static const struct dynamic_odt single_S[4] = {
322 static const struct dynamic_odt dual_DD[4] = {
325 FSL_DDR_ODT_SAME_DIMM,
330 FSL_DDR_ODT_OTHER_DIMM,
331 FSL_DDR_ODT_OTHER_DIMM,
337 FSL_DDR_ODT_SAME_DIMM,
342 FSL_DDR_ODT_OTHER_DIMM,
343 FSL_DDR_ODT_OTHER_DIMM,
349 static const struct dynamic_odt dual_DS[4] = {
352 FSL_DDR_ODT_SAME_DIMM,
357 FSL_DDR_ODT_OTHER_DIMM,
358 FSL_DDR_ODT_OTHER_DIMM,
363 FSL_DDR_ODT_OTHER_DIMM,
370 static const struct dynamic_odt dual_SD[4] = {
372 FSL_DDR_ODT_OTHER_DIMM,
380 FSL_DDR_ODT_SAME_DIMM,
385 FSL_DDR_ODT_OTHER_DIMM,
386 FSL_DDR_ODT_OTHER_DIMM,
392 static const struct dynamic_odt dual_SS[4] = {
394 FSL_DDR_ODT_OTHER_DIMM,
401 FSL_DDR_ODT_OTHER_DIMM,
409 static const struct dynamic_odt dual_D0[4] = {
412 FSL_DDR_ODT_SAME_DIMM,
426 static const struct dynamic_odt dual_0D[4] = {
431 FSL_DDR_ODT_SAME_DIMM,
443 static const struct dynamic_odt dual_S0[4] = {
456 static const struct dynamic_odt dual_0S[4] = {
469 static const struct dynamic_odt odt_unknown[4] = {
495 #else /* CONFIG_SYS_FSL_DDR3 */
496 static const struct dynamic_odt single_Q[4] = {
503 static const struct dynamic_odt single_D[4] = {
520 static const struct dynamic_odt single_S[4] = {
532 static const struct dynamic_odt dual_DD[4] = {
534 FSL_DDR_ODT_OTHER_DIMM,
535 FSL_DDR_ODT_OTHER_DIMM,
546 FSL_DDR_ODT_OTHER_DIMM,
547 FSL_DDR_ODT_OTHER_DIMM,
559 static const struct dynamic_odt dual_DS[4] = {
561 FSL_DDR_ODT_OTHER_DIMM,
562 FSL_DDR_ODT_OTHER_DIMM,
573 FSL_DDR_ODT_OTHER_DIMM,
574 FSL_DDR_ODT_OTHER_DIMM,
581 static const struct dynamic_odt dual_SD[4] = {
583 FSL_DDR_ODT_OTHER_DIMM,
584 FSL_DDR_ODT_OTHER_DIMM,
590 FSL_DDR_ODT_OTHER_DIMM,
591 FSL_DDR_ODT_OTHER_DIMM,
603 static const struct dynamic_odt dual_SS[4] = {
605 FSL_DDR_ODT_OTHER_DIMM,
606 FSL_DDR_ODT_OTHER_DIMM,
612 FSL_DDR_ODT_OTHER_DIMM,
613 FSL_DDR_ODT_OTHER_DIMM,
620 static const struct dynamic_odt dual_D0[4] = {
637 static const struct dynamic_odt dual_0D[4] = {
654 static const struct dynamic_odt dual_S0[4] = {
667 static const struct dynamic_odt dual_0S[4] = {
680 static const struct dynamic_odt odt_unknown[4] = {
709 * Automatically seleect bank interleaving mode based on DIMMs
710 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
711 * This function only deal with one or two slots per controller.
713 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
715 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
716 if (pdimm[0].n_ranks == 4)
717 return FSL_DDR_CS0_CS1_CS2_CS3;
718 else if (pdimm[0].n_ranks == 2)
719 return FSL_DDR_CS0_CS1;
720 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
721 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
722 if (pdimm[0].n_ranks == 4)
723 return FSL_DDR_CS0_CS1_CS2_CS3;
725 if (pdimm[0].n_ranks == 2) {
726 if (pdimm[1].n_ranks == 2)
727 return FSL_DDR_CS0_CS1_CS2_CS3;
729 return FSL_DDR_CS0_CS1;
735 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
736 memctl_options_t *popts,
737 dimm_params_t *pdimm,
738 unsigned int ctrl_num)
741 char buffer[HWCONFIG_BUFFER_SIZE];
743 #if defined(CONFIG_SYS_FSL_DDR3) || \
744 defined(CONFIG_SYS_FSL_DDR2) || \
745 defined(CONFIG_SYS_FSL_DDR4)
746 const struct dynamic_odt *pdodt = odt_unknown;
751 * Extract hwconfig from environment since we have not properly setup
752 * the environment but need it for ddr config params
754 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
757 #if defined(CONFIG_SYS_FSL_DDR3) || \
758 defined(CONFIG_SYS_FSL_DDR2) || \
759 defined(CONFIG_SYS_FSL_DDR4)
760 /* Chip select options. */
761 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
762 switch (pdimm[0].n_ranks) {
773 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
774 switch (pdimm[0].n_ranks) {
775 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
778 if (pdimm[1].n_ranks)
779 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
783 switch (pdimm[1].n_ranks) {
796 switch (pdimm[1].n_ranks) {
809 switch (pdimm[1].n_ranks) {
819 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
820 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
822 /* Pick chip-select local options. */
823 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
824 #if defined(CONFIG_SYS_FSL_DDR3) || \
825 defined(CONFIG_SYS_FSL_DDR2) || \
826 defined(CONFIG_SYS_FSL_DDR4)
827 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
828 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
829 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
830 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
832 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
833 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
835 popts->cs_local_opts[i].auto_precharge = 0;
838 /* Pick interleaving mode. */
841 * 0 = no interleaving
842 * 1 = interleaving between 2 controllers
844 popts->memctl_interleaving = 0;
850 * 3 = superbank (only if CS interleaving is enabled)
852 popts->memctl_interleaving_mode = 0;
855 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
856 * 1: page: bit to the left of the column bits selects the memctl
857 * 2: bank: bit to the left of the bank bits selects the memctl
858 * 3: superbank: bit to the left of the chip select selects the memctl
860 * NOTE: ba_intlv (rank interleaving) is independent of memory
861 * controller interleaving; it is only within a memory controller.
862 * Must use superbank interleaving if rank interleaving is used and
863 * memory controller interleaving is enabled.
870 * 0x60 = CS0,CS1 + CS2,CS3
871 * 0x04 = CS0,CS1,CS2,CS3
873 popts->ba_intlv_ctl = 0;
875 /* Memory Organization Parameters */
876 popts->registered_dimm_en = common_dimm->all_dimms_registered;
878 /* Operational Mode Paramters */
881 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
882 #ifdef CONFIG_DDR_ECC
883 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
884 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
889 popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
896 #if defined(CONFIG_SYS_FSL_DDR1)
897 popts->dqs_config = 0;
898 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
899 popts->dqs_config = 1;
902 /* Choose self-refresh during sleep. */
903 popts->self_refresh_in_sleep = 1;
905 /* Choose dynamic power management mode. */
906 popts->dynamic_power = 0;
909 * check first dimm for primary sdram width
910 * presuming all dimms are similar
911 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
913 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
914 if (pdimm[0].n_ranks != 0) {
915 if ((pdimm[0].data_width >= 64) && \
916 (pdimm[0].data_width <= 72))
917 popts->data_bus_width = 0;
918 else if ((pdimm[0].data_width >= 32) || \
919 (pdimm[0].data_width <= 40))
920 popts->data_bus_width = 1;
922 panic("Error: data width %u is invalid!\n",
923 pdimm[0].data_width);
927 if (pdimm[0].n_ranks != 0) {
928 if (pdimm[0].primary_sdram_width == 64)
929 popts->data_bus_width = 0;
930 else if (pdimm[0].primary_sdram_width == 32)
931 popts->data_bus_width = 1;
932 else if (pdimm[0].primary_sdram_width == 16)
933 popts->data_bus_width = 2;
935 panic("Error: primary sdram width %u is invalid!\n",
936 pdimm[0].primary_sdram_width);
941 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
943 /* Choose burst length. */
944 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
945 #if defined(CONFIG_E500MC)
946 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
947 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
949 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
950 /* 32-bit or 16-bit bus */
951 popts->otf_burst_chop_en = 0;
952 popts->burst_length = DDR_BL8;
954 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
955 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
959 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
962 /* Choose ddr controller address mirror mode */
963 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
964 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
965 if (pdimm[i].n_ranks) {
966 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
972 /* Global Timing Parameters. */
973 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
975 /* Pick a caslat override. */
976 popts->cas_latency_override = 0;
977 popts->cas_latency_override_value = 3;
978 if (popts->cas_latency_override) {
979 debug("using caslat override value = %u\n",
980 popts->cas_latency_override_value);
983 /* Decide whether to use the computed derated latency */
984 popts->use_derated_caslat = 0;
986 /* Choose an additive latency. */
987 popts->additive_latency_override = 0;
988 popts->additive_latency_override_value = 3;
989 if (popts->additive_latency_override) {
990 debug("using additive latency override value = %u\n",
991 popts->additive_latency_override_value);
997 * Factors to consider for 2T_EN:
998 * - number of DIMMs installed
999 * - number of components, number of active ranks
1000 * - how much time you want to spend playing around
1003 popts->threet_en = 0;
1005 /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
1006 if (popts->registered_dimm_en)
1007 popts->ap_en = 1; /* 0 = disable, 1 = enable */
1009 popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
1011 if (hwconfig_sub_f("fsl_ddr", "parity", buf)) {
1012 if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) {
1013 if (popts->registered_dimm_en ||
1014 (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4))
1020 * BSTTOPRE precharge interval
1022 * Set this to 0 for global auto precharge
1023 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
1024 * It is not wrong. Any value should be OK. The performance depends on
1025 * applications. There is no one good value for all. One way to set
1026 * is to use 1/4 of refint value.
1028 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
1032 * Window for four activates -- tFAW
1034 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
1035 * FIXME: varies depending upon number of column addresses or data
1036 * FIXME: width, was considering looking at pdimm->primary_sdram_width
1038 #if defined(CONFIG_SYS_FSL_DDR1)
1039 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
1041 #elif defined(CONFIG_SYS_FSL_DDR2)
1043 * x4/x8; some datasheets have 35000
1044 * x16 wide columns only? Use 50000?
1046 popts->tfaw_window_four_activates_ps = 37500;
1049 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
1052 popts->wrlvl_en = 0;
1053 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1055 * due to ddr3 dimm is fly-by topology
1056 * we suggest to enable write leveling to
1057 * meet the tQDSS under different loading.
1059 popts->wrlvl_en = 1;
1061 popts->wrlvl_override = 0;
1065 * Check interleaving configuration from environment.
1066 * Please refer to doc/README.fsl-ddr for the detail.
1068 * If memory controller interleaving is enabled, then the data
1069 * bus widths must be programmed identically for all memory controllers.
1071 * Attempt to set all controllers to the same chip select
1072 * interleaving mode. It will do a best effort to get the
1073 * requested ranks interleaved together such that the result
1074 * should be a subset of the requested configuration.
1076 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
1077 * with 256 Byte is enabled.
1079 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1080 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
1081 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1086 if (pdimm[0].n_ranks == 0) {
1087 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
1088 popts->memctl_interleaving = 0;
1091 popts->memctl_interleaving = 1;
1092 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
1093 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
1094 popts->memctl_interleaving = 1;
1095 debug("256 Byte interleaving\n");
1098 * test null first. if CONFIG_HWCONFIG is not defined
1099 * hwconfig_arg_cmp returns non-zero
1101 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
1103 popts->memctl_interleaving = 0;
1104 debug("memory controller interleaving disabled.\n");
1105 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1107 "cacheline", buf)) {
1108 popts->memctl_interleaving_mode =
1109 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1110 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
1111 popts->memctl_interleaving =
1112 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1114 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1117 popts->memctl_interleaving_mode =
1118 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1119 0 : FSL_DDR_PAGE_INTERLEAVING;
1120 popts->memctl_interleaving =
1121 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1123 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1126 popts->memctl_interleaving_mode =
1127 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1128 0 : FSL_DDR_BANK_INTERLEAVING;
1129 popts->memctl_interleaving =
1130 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1132 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1134 "superbank", buf)) {
1135 popts->memctl_interleaving_mode =
1136 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1137 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
1138 popts->memctl_interleaving =
1139 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
1141 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
1142 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1145 popts->memctl_interleaving_mode =
1146 FSL_DDR_3WAY_1KB_INTERLEAVING;
1147 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1150 popts->memctl_interleaving_mode =
1151 FSL_DDR_3WAY_4KB_INTERLEAVING;
1152 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1155 popts->memctl_interleaving_mode =
1156 FSL_DDR_3WAY_8KB_INTERLEAVING;
1157 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
1158 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1161 popts->memctl_interleaving_mode =
1162 FSL_DDR_4WAY_1KB_INTERLEAVING;
1163 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1166 popts->memctl_interleaving_mode =
1167 FSL_DDR_4WAY_4KB_INTERLEAVING;
1168 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
1171 popts->memctl_interleaving_mode =
1172 FSL_DDR_4WAY_8KB_INTERLEAVING;
1175 popts->memctl_interleaving = 0;
1176 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
1178 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
1180 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1181 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
1182 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
1183 /* test null first. if CONFIG_HWCONFIG is not defined,
1184 * hwconfig_subarg_cmp_f returns non-zero */
1185 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1187 debug("bank interleaving disabled.\n");
1188 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1190 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
1191 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1193 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
1194 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1195 "cs0_cs1_and_cs2_cs3", buf))
1196 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
1197 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1198 "cs0_cs1_cs2_cs3", buf))
1199 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
1200 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
1202 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
1204 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
1205 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1206 case FSL_DDR_CS0_CS1_CS2_CS3:
1207 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1208 if (pdimm[0].n_ranks < 4) {
1209 popts->ba_intlv_ctl = 0;
1210 printf("Not enough bank(chip-select) for "
1211 "CS0+CS1+CS2+CS3 on controller %d, "
1212 "interleaving disabled!\n", ctrl_num);
1214 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1215 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
1216 if (pdimm[0].n_ranks == 4)
1219 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
1220 popts->ba_intlv_ctl = 0;
1221 printf("Not enough bank(chip-select) for "
1222 "CS0+CS1+CS2+CS3 on controller %d, "
1223 "interleaving disabled!\n", ctrl_num);
1225 if (pdimm[0].capacity != pdimm[1].capacity) {
1226 popts->ba_intlv_ctl = 0;
1227 printf("Not identical DIMM size for "
1228 "CS0+CS1+CS2+CS3 on controller %d, "
1229 "interleaving disabled!\n", ctrl_num);
1233 case FSL_DDR_CS0_CS1:
1234 if (pdimm[0].n_ranks < 2) {
1235 popts->ba_intlv_ctl = 0;
1236 printf("Not enough bank(chip-select) for "
1237 "CS0+CS1 on controller %d, "
1238 "interleaving disabled!\n", ctrl_num);
1241 case FSL_DDR_CS2_CS3:
1242 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1243 if (pdimm[0].n_ranks < 4) {
1244 popts->ba_intlv_ctl = 0;
1245 printf("Not enough bank(chip-select) for CS2+CS3 "
1246 "on controller %d, interleaving disabled!\n", ctrl_num);
1248 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1249 if (pdimm[1].n_ranks < 2) {
1250 popts->ba_intlv_ctl = 0;
1251 printf("Not enough bank(chip-select) for CS2+CS3 "
1252 "on controller %d, interleaving disabled!\n", ctrl_num);
1256 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1257 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1258 if (pdimm[0].n_ranks < 4) {
1259 popts->ba_intlv_ctl = 0;
1260 printf("Not enough bank(CS) for CS0+CS1 and "
1261 "CS2+CS3 on controller %d, "
1262 "interleaving disabled!\n", ctrl_num);
1264 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1265 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1266 popts->ba_intlv_ctl = 0;
1267 printf("Not enough bank(CS) for CS0+CS1 and "
1268 "CS2+CS3 on controller %d, "
1269 "interleaving disabled!\n", ctrl_num);
1274 popts->ba_intlv_ctl = 0;
1279 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1280 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1281 popts->addr_hash = 0;
1282 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1284 popts->addr_hash = 1;
1287 if (pdimm[0].n_ranks == 4)
1288 popts->quad_rank_present = 1;
1290 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1291 if (popts->registered_dimm_en) {
1292 popts->rcw_override = 1;
1293 popts->rcw_1 = 0x000a5a00;
1294 if (ddr_freq <= 800)
1295 popts->rcw_2 = 0x00000000;
1296 else if (ddr_freq <= 1066)
1297 popts->rcw_2 = 0x00100000;
1298 else if (ddr_freq <= 1333)
1299 popts->rcw_2 = 0x00200000;
1301 popts->rcw_2 = 0x00300000;
1304 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1309 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1311 int i, j, k, check_n_ranks, intlv_invalid = 0;
1312 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1313 unsigned long long check_rank_density;
1314 struct dimm_params_s *dimm;
1315 int first_ctrl = pinfo->first_ctrl;
1316 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1319 * Check if all controllers are configured for memory
1320 * controller interleaving. Identical dimms are recommended. At least
1321 * the size, row and col address should be checked.
1324 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1325 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1326 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1327 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1328 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1329 for (i = first_ctrl; i <= last_ctrl; i++) {
1330 dimm = &pinfo->dimm_params[i][0];
1331 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1333 } else if (((check_rank_density != dimm->rank_density) ||
1334 (check_n_ranks != dimm->n_ranks) ||
1335 (check_n_row_addr != dimm->n_row_addr) ||
1336 (check_n_col_addr != dimm->n_col_addr) ||
1338 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1346 if (intlv_invalid) {
1347 for (i = first_ctrl; i <= last_ctrl; i++)
1348 pinfo->memctl_opts[i].memctl_interleaving = 0;
1349 printf("Not all DIMMs are identical. "
1350 "Memory controller interleaving disabled.\n");
1352 switch (check_intlv) {
1353 case FSL_DDR_256B_INTERLEAVING:
1354 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1355 case FSL_DDR_PAGE_INTERLEAVING:
1356 case FSL_DDR_BANK_INTERLEAVING:
1357 case FSL_DDR_SUPERBANK_INTERLEAVING:
1358 #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1361 k = CONFIG_NUM_DDR_CONTROLLERS;
1364 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1365 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1366 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1367 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1368 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1369 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1371 k = CONFIG_NUM_DDR_CONTROLLERS;
1374 debug("%d of %d controllers are interleaving.\n", j, k);
1375 if (j && (j != k)) {
1376 for (i = first_ctrl; i <= last_ctrl; i++)
1377 pinfo->memctl_opts[i].memctl_interleaving = 0;
1378 if ((last_ctrl - first_ctrl) > 1)
1379 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1382 debug("Checking interleaving options completed\n");
1385 int fsl_use_spd(void)
1389 #ifdef CONFIG_DDR_SPD
1390 char buffer[HWCONFIG_BUFFER_SIZE];
1394 * Extract hwconfig from environment since we have not properly setup
1395 * the environment but need it for ddr config params
1397 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1400 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1401 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1402 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1404 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",