1 /* ====================================================================
2 * Copyright (c) 2005 The OpenSSL Project. Rights for redistribution
3 * and usage in source and binary forms are granted according to the
13 const void *FIPS_text_start(void);
14 const void *FIPS_text_end(void);
18 #if !defined(POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION)
19 # if (defined(__sun) && (defined(__sparc) || defined(__sparcv9))) || \
20 (defined(__sgi) && (defined(__mips) || defined(mips))) || \
21 (defined(__osf__) && defined(__alpha)) || \
22 (defined(__linux) && (defined(__arm) || defined(__arm__))) || \
23 (defined(__i386) || defined(__i386__)) || \
24 (defined(__x86_64) || defined(__x86_64__)) || \
25 (defined(vax) || defined(__vax__))
26 # define POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION
30 #if !defined(FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE)
31 # if (defined(__ANDROID__) && (defined(__arm__) || defined(__arm) || \
32 defined(__i386__)|| defined(__i386))) || \
33 (defined(__vxworks) && (defined(__ppc__) || defined(__ppc) || \
34 defined(__mips__)|| defined(__mips))) || \
35 (defined(__linux) && ((defined(__PPC__) && !defined(__PPC64__)) || \
36 defined(__arm__) || defined(__arm)))
37 # define FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
41 #if defined(__xlC__) && __xlC__>=0x600 && (defined(_POWER) || defined(_ARCH_PPC))
42 static void *instruction_pointer_xlc(void);
43 # pragma mc_func instruction_pointer_xlc {\
44 "7c0802a6" /* mflr r0 */ \
45 "48000005" /* bl $+4 */ \
46 "7c6802a6" /* mflr r3 */ \
47 "7c0803a6" /* mtlr r0 */ }
48 # pragma reg_killed_by instruction_pointer_xlc gr0 gr3
49 # define INSTRUCTION_POINTER_IMPLEMENTED(ret) (ret=instruction_pointer_xlc());
53 # define FIPS_ref_point FIPS_text_start
54 # ifdef FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
55 # define instruction_pointer FIPS_text_startX
57 /* Some compilers put string literals into a separate segment. As we
58 * are mostly interested to hash AES tables in .rodata, we declare
59 * reference points accordingly. In case you wonder, the values are
60 * big-endian encoded variable names, just to prevent these arrays
61 * from being merged by linker. */
62 # if defined(_MSC_VER)
63 # pragma code_seg("fipstx")
65 __declspec(allocate("fipstx"))
66 const unsigned int FIPS_text_startX[]=
67 { 0x46495053, 0x5f746578, 0x745f7374, 0x61727458 };
68 # pragma const_seg("fipsro$a")
70 __declspec(allocate("fipsro$a"))
72 const unsigned int FIPS_rodata_start[]=
73 { 0x46495053, 0x5f726f64, 0x6174615f, 0x73746172 };
75 # define FIPS_ref_point FIPS_text_end
76 # ifdef FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
77 # define instruction_pointer FIPS_text_endX
79 # if defined(_MSC_VER)
80 # pragma code_seg("fipstx$z")
82 __declspec(allocate("fipstx$z"))
83 const unsigned int FIPS_text_endX[]=
84 { 0x46495053, 0x5f746578, 0x745f656e, 0x64585b5d };
85 # pragma const_seg("fipsro$z")
87 __declspec(allocate("fipsro$z"))
89 const unsigned int FIPS_rodata_end[]=
90 { 0x46495053, 0x5f726f64, 0x6174615f, 0x656e645b };
93 #if !defined(_MSC_VER) || !defined(instruction_pointer)
95 * I declare reference function as static in order to avoid certain
96 * pitfalls in -dynamic linker behaviour...
98 static void *instruction_pointer(void)
100 /* These are ABI-neutral CPU-specific snippets. ABI-neutrality means
101 * that they are designed to work under any OS running on particular
102 * CPU, which is why you don't find any #ifdef THIS_OR_THAT_OS in
104 #if defined(INSTRUCTION_POINTER_IMPLEMENTED)
105 INSTRUCTION_POINTER_IMPLEMENTED(ret);
106 #elif defined(__GNUC__) && __GNUC__>=2
107 # if defined(__alpha) || defined(__alpha__)
108 # define INSTRUCTION_POINTER_IMPLEMENTED
109 __asm __volatile ( "br %0,1f\n1:" : "=r"(ret) );
110 # elif defined(__i386) || defined(__i386__)
111 # define INSTRUCTION_POINTER_IMPLEMENTED
112 __asm __volatile ( "call 1f\n1: popl %0" : "=r"(ret) );
113 ret = (void *)((size_t)ret&~3UL); /* align for better performance */
114 # elif defined(__ia64) || defined(__ia64__)
115 # define INSTRUCTION_POINTER_IMPLEMENTED
116 __asm __volatile ( "mov %0=ip" : "=r"(ret) );
117 # elif defined(__hppa) || defined(__hppa__) || defined(__pa_risc)
118 # define INSTRUCTION_POINTER_IMPLEMENTED
119 __asm __volatile ( "blr %%r0,%0\n\tnop" : "=r"(ret) );
120 ret = (void *)((size_t)ret&~3UL); /* mask privilege level */
121 # elif defined(__mips) || defined(__mips__)
122 # define INSTRUCTION_POINTER_IMPLEMENTED
124 __asm __volatile ( "move %1,$31\n\t" /* save ra */
127 "move $31,%1" /* restore ra */
128 : "=r"(ret),"=r"(scratch) );
129 # elif defined(__ppc__) || defined(__ppc) || \
130 defined(__powerpc) || defined(__powerpc__) || \
131 defined(__POWERPC__) || defined(_POWER) || defined(__PPC__) || \
132 defined(__PPC64__) || defined(__ppc64__) || defined(__powerpc64__)
133 # define INSTRUCTION_POINTER_IMPLEMENTED
135 __asm __volatile ( "mfspr %1,8\n\t" /* save lr */
137 "mfspr %0,8\n\t" /* mflr ret */
138 "mtspr 8,%1" /* restore lr */
139 : "=r"(ret),"=r"(scratch) );
140 # elif defined(__s390__) || defined(__s390x__)
141 # define INSTRUCTION_POINTER_IMPLEMENTED
142 __asm __volatile ( "bras %0,1f\n1:" : "=r"(ret) );
143 ret = (void *)((size_t)ret&~3UL);
144 # elif defined(__sparc) || defined(__sparc__) || defined(__sparcv9)
145 # define INSTRUCTION_POINTER_IMPLEMENTED
147 __asm __volatile ( "mov %%o7,%1\n\t"
151 : "=r"(ret),"=r"(scratch) );
152 # elif defined(__x86_64) || defined(__x86_64__)
153 # define INSTRUCTION_POINTER_IMPLEMENTED
154 __asm __volatile ( "leaq 0(%%rip),%0" : "=r"(ret) );
155 ret = (void *)((size_t)ret&~3UL); /* align for better performance */
156 # elif defined(__arm) || defined(__arm__)
157 # define INSTRUCTION_POINTER_IMPLEMENTED
158 __asm __volatile ( "sub %0,pc,#8" : "=r"(ret) );
160 #elif defined(__DECC) && defined(__alpha)
161 # define INSTRUCTION_POINTER_IMPLEMENTED
162 ret = (void *)(size_t)asm("br %v0,1f\n1:");
163 #elif defined(_MSC_VER) && defined(_M_IX86)
164 # define INSTRUCTION_POINTER_IMPLEMENTED
171 ret = (void *)((size_t)scratch&~3UL);
178 * This function returns pointer to an instruction in the vicinity of
179 * its entry point, but not outside this object module. This guarantees
180 * that sequestered code is covered...
182 const void *FIPS_ref_point()
184 #if defined(FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE)
185 # if defined(__thumb__) || defined(__thumb)
186 return (void *)((size_t)instruction_pointer&~1);
188 return (void *)instruction_pointer;
190 #elif defined(INSTRUCTION_POINTER_IMPLEMENTED)
191 return instruction_pointer();
192 /* Below we essentially cover vendor compilers which do not support
193 * inline assembler... */
195 struct { void *ip,*gp,*env; } *p = (void *)instruction_pointer;
197 #elif defined(_HPUX_SOURCE)
198 # if defined(__hppa) || defined(__hppa__)
199 struct { void *i[4]; } *p = (void *)FIPS_ref_point;
201 if (sizeof(p) == 8) /* 64-bit */
203 else if ((size_t)p & 2)
204 { p = (void *)((size_t)p&~3UL);
209 # elif defined(__ia64) || defined(__ia64__)
210 struct { unsigned long long ip,gp; } *p=(void *)instruction_pointer;
211 return (void *)(size_t)p->ip;
213 #elif (defined(__VMS) || defined(VMS)) && !(defined(vax) || defined(__vax__))
214 /* applies to both alpha and ia64 */
215 struct { unsigned __int64 opaque,ip; } *p=(void *)instruction_pointer;
216 return (void *)(size_t)p->ip;
217 #elif defined(__VOS__)
218 /* applies to both pa-risc and ia32 */
219 struct { void *dp,*ip,*gp; } *p = (void *)instruction_pointer;
221 #elif defined(_WIN32)
222 # if defined(_WIN64) && defined(_M_IA64)
223 struct { void *ip,*gp; } *p = (void *)FIPS_ref_point;
226 return (void *)FIPS_ref_point;
229 * In case you wonder why there is no #ifdef __linux. All Linux targets
230 * are GCC-based and therefore are covered by instruction_pointer above
231 * [well, some are covered by by the one below]...
233 #elif defined(POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION)
234 return (void *)instruction_pointer;