1 /* ====================================================================
2 * Copyright (c) 2005 The OpenSSL Project. Rights for redistribution
3 * and usage in source and binary forms are granted according to the
13 const void *FIPS_text_start(void);
14 const void *FIPS_text_end(void);
18 #if !defined(POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION)
19 # if (defined(__sun) && (defined(__sparc) || defined(__sparcv9))) || \
20 (defined(__sgi) && (defined(__mips) || defined(mips))) || \
21 (defined(__osf__) && defined(__alpha)) || \
22 (defined(__linux) && (defined(__arm) || defined(__arm__))) || \
23 (defined(__i386) || defined(__i386__)) || \
24 (defined(__x86_64) || defined(__x86_64__)) || \
25 (defined(vax) || defined(__vax__))
26 # define POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION
30 #if !defined(FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE)
31 # if (defined(__ANDROID__) && (defined(__arm__) || defined(__arm) || \
32 defined(__i386__)|| defined(__i386))) || \
33 (defined(__vxworks) && (defined(__ppc__) || defined(__ppc) || \
34 defined(__mips__)|| defined(__mips))) || \
35 (defined(__linux) && ((defined(__PPC__) && !defined(__PPC64__)) || \
36 defined(__arm__) || defined(__arm)))
37 # define FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
41 #if defined(__xlC__) && __xlC__>=0x600 && (defined(_POWER) || defined(_ARCH_PPC))
42 static void *instruction_pointer_xlc(void);
43 # pragma mc_func instruction_pointer_xlc {\
44 "7c0802a6" /* mflr r0 */ \
45 "48000005" /* bl $+4 */ \
46 "7c6802a6" /* mflr r3 */ \
47 "7c0803a6" /* mtlr r0 */ }
48 # pragma reg_killed_by instruction_pointer_xlc gr0 gr3
49 # define INSTRUCTION_POINTER_IMPLEMENTED(ret) (ret=instruction_pointer_xlc());
53 # define FIPS_ref_point FIPS_text_start
54 # ifdef FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
55 # define instruction_pointer FIPS_text_startX
57 /* Some compilers put string literals into a separate segment. As we
58 * are mostly interested to hash AES tables in .rodata, we declare
59 * reference points accordingly. In case you wonder, the values are
60 * big-endian encoded variable names, just to prevent these arrays
61 * from being merged by linker. */
62 # if defined(_MSC_VER)
63 # pragma section("fipsro$a",read)
64 __declspec(allocate("fipsro$a"))
66 const unsigned int FIPS_rodata_start[]=
67 { 0x46495053, 0x5f726f64, 0x6174615f, 0x73746172 };
69 # define FIPS_ref_point FIPS_text_end
70 # ifdef FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE
71 # define instruction_pointer FIPS_text_endX
73 # if defined(_MSC_VER)
74 # pragma section("fipsro$c",read)
75 __declspec(allocate("fipsro$c"))
77 const unsigned int FIPS_rodata_end[]=
78 { 0x46495053, 0x5f726f64, 0x6174615f, 0x656e645b };
82 * I declare reference function as static in order to avoid certain
83 * pitfalls in -dynamic linker behaviour...
85 static void *instruction_pointer(void)
87 /* These are ABI-neutral CPU-specific snippets. ABI-neutrality means
88 * that they are designed to work under any OS running on particular
89 * CPU, which is why you don't find any #ifdef THIS_OR_THAT_OS in
91 #if defined(INSTRUCTION_POINTER_IMPLEMENTED)
92 INSTRUCTION_POINTER_IMPLEMENTED(ret);
93 #elif defined(__GNUC__) && __GNUC__>=2
94 # if defined(__alpha) || defined(__alpha__)
95 # define INSTRUCTION_POINTER_IMPLEMENTED
96 __asm __volatile ( "br %0,1f\n1:" : "=r"(ret) );
97 # elif defined(__i386) || defined(__i386__)
98 # define INSTRUCTION_POINTER_IMPLEMENTED
99 __asm __volatile ( "call 1f\n1: popl %0" : "=r"(ret) );
100 ret = (void *)((size_t)ret&~3UL); /* align for better performance */
101 # elif defined(__ia64) || defined(__ia64__)
102 # define INSTRUCTION_POINTER_IMPLEMENTED
103 __asm __volatile ( "mov %0=ip" : "=r"(ret) );
104 # elif defined(__hppa) || defined(__hppa__) || defined(__pa_risc)
105 # define INSTRUCTION_POINTER_IMPLEMENTED
106 __asm __volatile ( "blr %%r0,%0\n\tnop" : "=r"(ret) );
107 ret = (void *)((size_t)ret&~3UL); /* mask privilege level */
108 # elif defined(__mips) || defined(__mips__)
109 # define INSTRUCTION_POINTER_IMPLEMENTED
111 __asm __volatile ( "move %1,$31\n\t" /* save ra */
114 "move $31,%1" /* restore ra */
115 : "=r"(ret),"=r"(scratch) );
116 # elif defined(__ppc__) || defined(__ppc) || \
117 defined(__powerpc) || defined(__powerpc__) || \
118 defined(__POWERPC__) || defined(_POWER) || defined(__PPC__) || \
119 defined(__PPC64__) || defined(__ppc64__) || defined(__powerpc64__)
120 # define INSTRUCTION_POINTER_IMPLEMENTED
122 __asm __volatile ( "mfspr %1,8\n\t" /* save lr */
124 "mfspr %0,8\n\t" /* mflr ret */
125 "mtspr 8,%1" /* restore lr */
126 : "=r"(ret),"=r"(scratch) );
127 # elif defined(__s390__) || defined(__s390x__)
128 # define INSTRUCTION_POINTER_IMPLEMENTED
129 __asm __volatile ( "bras %0,1f\n1:" : "=r"(ret) );
130 ret = (void *)((size_t)ret&~3UL);
131 # elif defined(__sparc) || defined(__sparc__) || defined(__sparcv9)
132 # define INSTRUCTION_POINTER_IMPLEMENTED
134 __asm __volatile ( "mov %%o7,%1\n\t"
138 : "=r"(ret),"=r"(scratch) );
139 # elif defined(__x86_64) || defined(__x86_64__)
140 # define INSTRUCTION_POINTER_IMPLEMENTED
141 __asm __volatile ( "leaq 0(%%rip),%0" : "=r"(ret) );
142 ret = (void *)((size_t)ret&~3UL); /* align for better performance */
143 # elif defined(__arm) || defined(__arm__)
144 # define INSTRUCTION_POINTER_IMPLEMENTED
145 __asm __volatile ( "sub %0,pc,#8" : "=r"(ret) );
147 #elif defined(__DECC) && defined(__alpha)
148 # define INSTRUCTION_POINTER_IMPLEMENTED
149 ret = (void *)(size_t)asm("br %v0,1f\n1:");
150 #elif defined(_MSC_VER) && defined(_M_IX86)
151 # define INSTRUCTION_POINTER_IMPLEMENTED
158 ret = (void *)((size_t)scratch&~3UL);
164 * This function returns pointer to an instruction in the vicinity of
165 * its entry point, but not outside this object module. This guarantees
166 * that sequestered code is covered...
168 const void *FIPS_ref_point()
170 #if defined(FIPS_REF_POINT_IS_CROSS_COMPILER_AWARE)
171 # if defined(__thumb__) || defined(__thumb)
172 return (void *)((size_t)instruction_pointer&~1);
174 return (void *)instruction_pointer;
176 #elif defined(INSTRUCTION_POINTER_IMPLEMENTED)
177 return instruction_pointer();
178 /* Below we essentially cover vendor compilers which do not support
179 * inline assembler... */
181 struct { void *ip,*gp,*env; } *p = (void *)instruction_pointer;
183 #elif defined(_HPUX_SOURCE)
184 # if defined(__hppa) || defined(__hppa__)
185 struct { void *i[4]; } *p = (void *)FIPS_ref_point;
187 if (sizeof(p) == 8) /* 64-bit */
189 else if ((size_t)p & 2)
190 { p = (void *)((size_t)p&~3UL);
195 # elif defined(__ia64) || defined(__ia64__)
196 struct { unsigned long long ip,gp; } *p=(void *)instruction_pointer;
197 return (void *)(size_t)p->ip;
199 #elif (defined(__VMS) || defined(VMS)) && !(defined(vax) || defined(__vax__))
200 /* applies to both alpha and ia64 */
201 struct { unsigned __int64 opaque,ip; } *p=(void *)instruction_pointer;
202 return (void *)(size_t)p->ip;
203 #elif defined(__VOS__)
204 /* applies to both pa-risc and ia32 */
205 struct { void *dp,*ip,*gp; } *p = (void *)instruction_pointer;
207 #elif defined(_WIN32)
208 # if defined(_WIN64) && defined(_M_IA64)
209 struct { void *ip,*gp; } *p = (void *)FIPS_ref_point;
212 return (void *)FIPS_ref_point;
215 * In case you wonder why there is no #ifdef __linux. All Linux targets
216 * are GCC-based and therefore are covered by instruction_pointer above
217 * [well, some are covered by by the one below]...
219 #elif defined(POINTER_TO_FUNCTION_IS_POINTER_TO_1ST_INSTRUCTION)
220 return (void *)instruction_pointer;