1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx AXI platforms watchdog timer driver.
5 * Author(s): Michal Simek <michal.simek@xilinx.com>
6 * Shreenidhi Shedi <yesshedi@gmail.com>
8 * Copyright (c) 2011-2018 Xilinx Inc.
14 #include <linux/err.h>
17 #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */
18 #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */
19 #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/
20 #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */
22 struct watchdog_regs {
28 struct xlnx_wdt_platdata {
30 struct watchdog_regs *regs;
33 static int xlnx_wdt_reset(struct udevice *dev)
36 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
38 debug("%s ", __func__);
40 /* Read the current contents of TCSR0 */
41 reg = readl(&platdata->regs->twcsr0);
43 /* Clear the watchdog WDS bit */
44 if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK))
45 writel(reg | XWT_CSR0_WDS_MASK, &platdata->regs->twcsr0);
50 static int xlnx_wdt_stop(struct udevice *dev)
53 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
55 if (platdata->enable_once) {
56 debug("Can't stop Xilinx watchdog.\n");
60 /* Read the current contents of TCSR0 */
61 reg = readl(&platdata->regs->twcsr0);
63 writel(reg & ~XWT_CSR0_EWDT1_MASK, &platdata->regs->twcsr0);
64 writel(~XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
66 debug("Watchdog disabled!\n");
71 static int xlnx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
73 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
75 debug("%s:\n", __func__);
77 writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK),
78 &platdata->regs->twcsr0);
80 writel(XWT_CSRX_EWDT2_MASK, &platdata->regs->twcsr1);
85 static int xlnx_wdt_probe(struct udevice *dev)
87 debug("%s: Probing wdt%u\n", __func__, dev->seq);
92 static int xlnx_wdt_ofdata_to_platdata(struct udevice *dev)
94 struct xlnx_wdt_platdata *platdata = dev_get_platdata(dev);
96 platdata->regs = (struct watchdog_regs *)dev_read_addr(dev);
97 if (IS_ERR(platdata->regs))
98 return PTR_ERR(platdata->regs);
100 platdata->enable_once = dev_read_u32_default(dev,
101 "xlnx,wdt-enable-once", 0);
103 debug("%s: wdt-enable-once %d\n", __func__, platdata->enable_once);
108 static const struct wdt_ops xlnx_wdt_ops = {
109 .start = xlnx_wdt_start,
110 .reset = xlnx_wdt_reset,
111 .stop = xlnx_wdt_stop,
114 static const struct udevice_id xlnx_wdt_ids[] = {
115 { .compatible = "xlnx,xps-timebase-wdt-1.00.a", },
116 { .compatible = "xlnx,xps-timebase-wdt-1.01.a", },
120 U_BOOT_DRIVER(xlnx_wdt) = {
123 .of_match = xlnx_wdt_ids,
124 .probe = xlnx_wdt_probe,
125 .platdata_auto_alloc_size = sizeof(struct xlnx_wdt_platdata),
126 .ofdata_to_platdata = xlnx_wdt_ofdata_to_platdata,
127 .ops = &xlnx_wdt_ops,