1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
12 #include <linux/iopoll.h>
15 #define IWDG_KR 0x00 /* Key register */
16 #define IWDG_PR 0x04 /* Prescaler Register */
17 #define IWDG_RLR 0x08 /* ReLoad Register */
18 #define IWDG_SR 0x0C /* Status Register */
20 /* IWDG_KR register bit mask */
21 #define KR_KEY_RELOAD 0xAAAA /* Reload counter enable */
22 #define KR_KEY_ENABLE 0xCCCC /* Peripheral enable */
23 #define KR_KEY_EWA 0x5555 /* Write access enable */
25 /* IWDG_PR register bit values */
26 #define PR_256 0x06 /* Prescaler set to 256 */
28 /* IWDG_RLR register values */
29 #define RLR_MAX 0xFFF /* Max value supported by reload register */
31 /* IWDG_SR register bit values */
32 #define SR_PVU BIT(0) /* Watchdog prescaler value update */
33 #define SR_RVU BIT(1) /* Watchdog counter reload value update */
35 struct stm32mp_wdt_priv {
36 fdt_addr_t base; /* registers addr in physical memory */
37 unsigned long wdt_clk_rate; /* Watchdog dedicated clock rate */
40 static int stm32mp_wdt_reset(struct udevice *dev)
42 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
44 writel(KR_KEY_RELOAD, priv->base + IWDG_KR);
49 static int stm32mp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
51 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
56 /* Prescaler fixed to 256 */
57 reload = timeout_ms * priv->wdt_clk_rate / 256;
58 if (reload > RLR_MAX + 1)
59 /* Force to max watchdog counter reload value */
62 /* Force to min watchdog counter reload value */
63 reload = priv->wdt_clk_rate / 256;
65 /* Set prescaler & reload registers */
66 writel(KR_KEY_EWA, priv->base + IWDG_KR);
67 writel(PR_256, priv->base + IWDG_PR);
68 writel(reload - 1, priv->base + IWDG_RLR);
71 writel(KR_KEY_ENABLE, priv->base + IWDG_KR);
73 /* Wait for the registers to be updated */
74 ret = readl_poll_timeout(priv->base + IWDG_SR, val,
75 val & (SR_PVU | SR_RVU), CONFIG_SYS_HZ);
78 pr_err("Updating IWDG registers timeout");
85 static int stm32mp_wdt_probe(struct udevice *dev)
87 struct stm32mp_wdt_priv *priv = dev_get_priv(dev);
93 priv->base = devfdt_get_addr(dev);
94 if (priv->base == FDT_ADDR_T_NONE)
98 ret = clk_get_by_name(dev, "pclk", &clk);
102 ret = clk_enable(&clk);
107 ret = clk_get_by_name(dev, "lsi", &clk);
111 priv->wdt_clk_rate = clk_get_rate(&clk);
113 debug("IWDG init done\n");
118 static const struct wdt_ops stm32mp_wdt_ops = {
119 .start = stm32mp_wdt_start,
120 .reset = stm32mp_wdt_reset,
123 static const struct udevice_id stm32mp_wdt_match[] = {
124 { .compatible = "st,stm32mp1-iwdg" },
128 U_BOOT_DRIVER(stm32mp_wdt) = {
129 .name = "stm32mp-wdt",
131 .of_match = stm32mp_wdt_match,
132 .priv_auto_alloc_size = sizeof(struct stm32mp_wdt_priv),
133 .probe = stm32mp_wdt_probe,
134 .ops = &stm32mp_wdt_ops,