1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for SP805 on some Layerscape SoC
10 #include <dm/device.h>
11 #include <dm/fdtaddr.h>
13 #include <linux/bitops.h>
16 #include <linux/err.h>
19 #define WDTCONTROL 0x008
20 #define WDTINTCLR 0x00C
23 #define TIME_OUT_MIN_MSECS 1
24 #define TIME_OUT_MAX_MSECS 120000
25 #define SYS_FSL_WDT_CLK_DIV 16
26 #define INT_ENABLE BIT(0)
27 #define RESET_ENABLE BIT(1)
29 #define UNLOCK 0x1ACCE551
30 #define LOCK 0x00000001
31 #define INT_MASK BIT(0)
33 DECLARE_GLOBAL_DATA_PTR;
35 struct sp805_wdt_priv {
39 static int sp805_wdt_reset(struct udevice *dev)
41 struct sp805_wdt_priv *priv = dev_get_priv(dev);
43 writel(UNLOCK, priv->reg + WDTLOCK);
44 writel(INT_MASK, priv->reg + WDTINTCLR);
45 writel(LOCK, priv->reg + WDTLOCK);
46 readl(priv->reg + WDTLOCK);
51 static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
55 struct sp805_wdt_priv *priv = dev_get_priv(dev);
57 load_time = (u32)timeout;
58 if (timeout < TIME_OUT_MIN_MSECS)
59 load_time = TIME_OUT_MIN_MSECS;
60 else if (timeout > TIME_OUT_MAX_MSECS)
61 load_time = TIME_OUT_MAX_MSECS;
62 /* sp805 runs counter with given value twice, so when the max timeout is
63 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
66 load_value = (gd->bus_clk) /
67 (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
69 writel(UNLOCK, priv->reg + WDTLOCK);
70 writel(load_value, priv->reg + WDTLOAD);
71 writel(INT_MASK, priv->reg + WDTINTCLR);
72 writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
73 writel(LOCK, priv->reg + WDTLOCK);
74 readl(priv->reg + WDTLOCK);
79 static int sp805_wdt_stop(struct udevice *dev)
81 struct sp805_wdt_priv *priv = dev_get_priv(dev);
83 writel(UNLOCK, priv->reg + WDTLOCK);
84 writel(DISABLE, priv->reg + WDTCONTROL);
85 writel(LOCK, priv->reg + WDTLOCK);
86 readl(priv->reg + WDTLOCK);
91 static int sp805_wdt_expire_now(struct udevice *dev, ulong flags)
93 sp805_wdt_start(dev, 0, flags);
98 static int sp805_wdt_probe(struct udevice *dev)
100 debug("%s: Probing wdt%u (sp805-wdt)\n", __func__, dev->seq);
105 static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
107 struct sp805_wdt_priv *priv = dev_get_priv(dev);
109 priv->reg = (void __iomem *)dev_read_addr(dev);
110 if (IS_ERR(priv->reg))
111 return PTR_ERR(priv->reg);
116 static const struct wdt_ops sp805_wdt_ops = {
117 .start = sp805_wdt_start,
118 .reset = sp805_wdt_reset,
119 .stop = sp805_wdt_stop,
120 .expire_now = sp805_wdt_expire_now,
123 static const struct udevice_id sp805_wdt_ids[] = {
124 { .compatible = "arm,sp805-wdt" },
128 U_BOOT_DRIVER(sp805_wdt) = {
131 .of_match = sp805_wdt_ids,
132 .probe = sp805_wdt_probe,
133 .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
134 .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
135 .ops = &sp805_wdt_ops,