1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for SP805 on some Layerscape SoC
10 #include <dm/device.h>
11 #include <dm/fdtaddr.h>
13 #include <linux/bitops.h>
18 #define WDTCONTROL 0x008
19 #define WDTINTCLR 0x00C
22 #define TIME_OUT_MIN_MSECS 1
23 #define TIME_OUT_MAX_MSECS 120000
24 #define SYS_FSL_WDT_CLK_DIV 16
25 #define INT_ENABLE BIT(0)
26 #define RESET_ENABLE BIT(1)
28 #define UNLOCK 0x1ACCE551
29 #define LOCK 0x00000001
30 #define INT_MASK BIT(0)
32 DECLARE_GLOBAL_DATA_PTR;
34 struct sp805_wdt_priv {
38 static int sp805_wdt_reset(struct udevice *dev)
40 struct sp805_wdt_priv *priv = dev_get_priv(dev);
42 writel(UNLOCK, priv->reg + WDTLOCK);
43 writel(INT_MASK, priv->reg + WDTINTCLR);
44 writel(LOCK, priv->reg + WDTLOCK);
45 readl(priv->reg + WDTLOCK);
50 static int sp805_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
54 struct sp805_wdt_priv *priv = dev_get_priv(dev);
56 load_time = (u32)timeout;
57 if (timeout < TIME_OUT_MIN_MSECS)
58 load_time = TIME_OUT_MIN_MSECS;
59 else if (timeout > TIME_OUT_MAX_MSECS)
60 load_time = TIME_OUT_MAX_MSECS;
61 /* sp805 runs counter with given value twice, so when the max timeout is
62 * set 120s, the gd->bus_clk is less than 1145MHz, the load_value will
65 load_value = (gd->bus_clk) /
66 (2 * 1000 * SYS_FSL_WDT_CLK_DIV) * load_time;
68 writel(UNLOCK, priv->reg + WDTLOCK);
69 writel(load_value, priv->reg + WDTLOAD);
70 writel(INT_MASK, priv->reg + WDTINTCLR);
71 writel(INT_ENABLE | RESET_ENABLE, priv->reg + WDTCONTROL);
72 writel(LOCK, priv->reg + WDTLOCK);
73 readl(priv->reg + WDTLOCK);
78 static int sp805_wdt_stop(struct udevice *dev)
80 struct sp805_wdt_priv *priv = dev_get_priv(dev);
82 writel(UNLOCK, priv->reg + WDTLOCK);
83 writel(DISABLE, priv->reg + WDTCONTROL);
84 writel(LOCK, priv->reg + WDTLOCK);
85 readl(priv->reg + WDTLOCK);
90 static int sp805_wdt_probe(struct udevice *dev)
92 debug("%s: Probing wdt%u\n", __func__, dev->seq);
97 static int sp805_wdt_ofdata_to_platdata(struct udevice *dev)
99 struct sp805_wdt_priv *priv = dev_get_priv(dev);
101 priv->reg = (void __iomem *)dev_read_addr(dev);
102 if (IS_ERR(priv->reg))
103 return PTR_ERR(priv->reg);
108 static const struct wdt_ops sp805_wdt_ops = {
109 .start = sp805_wdt_start,
110 .reset = sp805_wdt_reset,
111 .stop = sp805_wdt_stop,
114 static const struct udevice_id sp805_wdt_ids[] = {
115 { .compatible = "arm,sp805-wdt" },
119 U_BOOT_DRIVER(sp805_wdt) = {
122 .of_match = sp805_wdt_ids,
123 .probe = sp805_wdt_probe,
124 .priv_auto_alloc_size = sizeof(struct sp805_wdt_priv),
125 .ofdata_to_platdata = sp805_wdt_ofdata_to_platdata,
126 .ops = &sp805_wdt_ops,