2 * watchdog.c - driver for i.mx on-chip watchdog
4 * Licensed under the GPL-2 or later.
10 #include <asm/arch/imx-regs.h>
11 #ifdef CONFIG_FSL_LSCH2
12 #include <asm/arch/immap_lsch2.h>
16 #ifdef CONFIG_IMX_WATCHDOG
17 void hw_watchdog_reset(void)
19 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
21 writew(0x5555, &wdog->wsr);
22 writew(0xaaaa, &wdog->wsr);
25 void hw_watchdog_init(void)
27 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
31 * The timer watchdog can be set between
32 * 0.5 and 128 Seconds. If not defined
33 * in configuration file, sets 128 Seconds
35 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
36 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
38 timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
39 #ifdef CONFIG_FSL_LSCH2
40 writew((WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout, &wdog->wcr);
42 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS |
43 WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr);
44 #endif /* CONFIG_FSL_LSCH2*/
49 void __attribute__((weak)) reset_cpu(ulong addr)
51 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
53 clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE);
55 writew(0x5555, &wdog->wsr);
56 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
59 * spin for .5 seconds before reset