drivers/watchdog/designware_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <wdt.h>
   9 #include <asm/io.h>
  10 #include <asm/utils.h>
  11
  12 #define DW_WDT_CR       0x00
  13 #define DW_WDT_TORR     0x04
  14 #define DW_WDT_CRR      0x0C
  15
  16 #define DW_WDT_CR_EN_OFFSET     0x00
  17 #define DW_WDT_CR_RMOD_OFFSET   0x01
  18 #define DW_WDT_CR_RMOD_VAL      0x00
  19 #define DW_WDT_CRR_RESTART_VAL  0x76
  20
  21 struct designware_wdt_priv {
  22         void __iomem    *base;
  23 };
  24
  25 /*
  26  * Set the watchdog time interval.
  27  * Counter is 32 bit.
  28  */
  29 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
  30                                      unsigned int timeout)
  31 {
  32         signed int i;
  33
  34         /* calculate the timeout range value */
  35         i = log_2_n_round_up(timeout * clk_khz) - 16;
  36         i = clamp(i, 0, 15);
  37
  38         writel(i | (i << 4), base + DW_WDT_TORR);
  39
  40         return 0;
  41 }
  42
  43 static void designware_wdt_enable(void __iomem *base)
  44 {
  45         writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
  46                 BIT(DW_WDT_CR_EN_OFFSET),
  47                 base + DW_WDT_CR);
  48 }
  49
  50 static unsigned int designware_wdt_is_enabled(void __iomem *base)
  51 {
  52         return readl(base + DW_WDT_CR) & BIT(0);
  53 }
  54
  55 static void designware_wdt_reset_common(void __iomem *base)
  56 {
  57         if (designware_wdt_is_enabled(base))
  58                 /* restart the watchdog counter */
  59                 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
  60 }
  61
  62 #if !CONFIG_IS_ENABLED(WDT)
  63 void hw_watchdog_reset(void)
  64 {
  65         designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
  66 }
  67
  68 void hw_watchdog_init(void)
  69 {
  70         /* reset to disable the watchdog */
  71         hw_watchdog_reset();
  72         /* set timer in miliseconds */
  73         designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
  74                                   CONFIG_DW_WDT_CLOCK_KHZ,
  75                                   CONFIG_WATCHDOG_TIMEOUT_MSECS);
  76         /* enable the watchdog */
  77         designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
  78         /* reset the watchdog */
  79         hw_watchdog_reset();
  80 }
  81 #else
  82 static int designware_wdt_reset(struct udevice *dev)
  83 {
  84         struct designware_wdt_priv *priv = dev_get_priv(dev);
  85
  86         designware_wdt_reset_common(priv->base);
  87
  88         return 0;
  89 }
  90
  91 static int designware_wdt_stop(struct udevice *dev)
  92 {
  93         struct designware_wdt_priv *priv = dev_get_priv(dev);
  94
  95         designware_wdt_reset(dev);
  96         writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
  97                 priv->base + DW_WDT_CR);
  98
  99         return 0;
 100 }
 101
 102 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
 103 {
 104         struct designware_wdt_priv *priv = dev_get_priv(dev);
 105
 106         designware_wdt_stop(dev);
 107
 108         /* set timer in miliseconds */
 109         designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
 110
 111         designware_wdt_enable(priv->base);
 112
 113         /* reset the watchdog */
 114         return designware_wdt_reset(dev);
 115 }
 116
 117 static int designware_wdt_probe(struct udevice *dev)
 118 {
 119         struct designware_wdt_priv *priv = dev_get_priv(dev);
 120
 121         priv->base = dev_remap_addr(dev);
 122         if (!priv->base)
 123                 return -EINVAL;
 124
 125         /* reset to disable the watchdog */
 126         return designware_wdt_stop(dev);
 127 }
 128
 129 static const struct wdt_ops designware_wdt_ops = {
 130         .start = designware_wdt_start,
 131         .reset = designware_wdt_reset,
 132         .stop = designware_wdt_stop,
 133 };
 134
 135 static const struct udevice_id designware_wdt_ids[] = {
 136         { .compatible = "snps,dw-wdt"},
 137         {}
 138 };
 139
 140 U_BOOT_DRIVER(designware_wdt) = {
 141         .name = "designware_wdt",
 142         .id = UCLASS_WDT,
 143         .of_match = designware_wdt_ids,
 144         .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
 145         .probe = designware_wdt_probe,
 146         .ops = &designware_wdt_ops,
 147         .flags = DM_FLAG_PRE_RELOC,
 148 };
 149 #endif