1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
12 #include <asm/utils.h>
14 #define DW_WDT_CR 0x00
15 #define DW_WDT_TORR 0x04
16 #define DW_WDT_CRR 0x0C
18 #define DW_WDT_CR_EN_OFFSET 0x00
19 #define DW_WDT_CR_RMOD_OFFSET 0x01
20 #define DW_WDT_CRR_RESTART_VAL 0x76
22 struct designware_wdt_priv {
28 * Set the watchdog time interval.
31 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
36 /* calculate the timeout range value */
37 i = log_2_n_round_up(timeout * clk_khz) - 16;
40 writel(i | (i << 4), base + DW_WDT_TORR);
45 static void designware_wdt_enable(void __iomem *base)
47 writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
50 static unsigned int designware_wdt_is_enabled(void __iomem *base)
52 return readl(base + DW_WDT_CR) & BIT(0);
55 static void designware_wdt_reset_common(void __iomem *base)
57 if (designware_wdt_is_enabled(base))
58 /* restart the watchdog counter */
59 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
62 #if !CONFIG_IS_ENABLED(WDT)
63 void hw_watchdog_reset(void)
65 designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
68 void hw_watchdog_init(void)
70 /* reset to disable the watchdog */
72 /* set timer in miliseconds */
73 designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
74 CONFIG_DW_WDT_CLOCK_KHZ,
75 CONFIG_WATCHDOG_TIMEOUT_MSECS);
76 /* enable the watchdog */
77 designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
78 /* reset the watchdog */
82 static int designware_wdt_reset(struct udevice *dev)
84 struct designware_wdt_priv *priv = dev_get_priv(dev);
86 designware_wdt_reset_common(priv->base);
91 static int designware_wdt_stop(struct udevice *dev)
93 struct designware_wdt_priv *priv = dev_get_priv(dev);
95 designware_wdt_reset(dev);
96 writel(0, priv->base + DW_WDT_CR);
101 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
103 struct designware_wdt_priv *priv = dev_get_priv(dev);
105 designware_wdt_stop(dev);
107 /* set timer in miliseconds */
108 designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
110 designware_wdt_enable(priv->base);
112 /* reset the watchdog */
113 return designware_wdt_reset(dev);
116 static int designware_wdt_probe(struct udevice *dev)
118 struct designware_wdt_priv *priv = dev_get_priv(dev);
119 __maybe_unused int ret;
121 priv->base = dev_remap_addr(dev);
125 #if CONFIG_IS_ENABLED(CLK)
128 ret = clk_get_by_index(dev, 0, &clk);
132 priv->clk_khz = clk_get_rate(&clk);
136 priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
139 #if CONFIG_IS_ENABLED(DM_RESET)
140 struct reset_ctl_bulk resets;
142 ret = reset_get_bulk(dev, &resets);
146 ret = reset_deassert_bulk(&resets);
151 /* reset to disable the watchdog */
152 return designware_wdt_stop(dev);
155 static const struct wdt_ops designware_wdt_ops = {
156 .start = designware_wdt_start,
157 .reset = designware_wdt_reset,
158 .stop = designware_wdt_stop,
161 static const struct udevice_id designware_wdt_ids[] = {
162 { .compatible = "snps,dw-wdt"},
166 U_BOOT_DRIVER(designware_wdt) = {
167 .name = "designware_wdt",
169 .of_match = designware_wdt_ids,
170 .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
171 .probe = designware_wdt_probe,
172 .ops = &designware_wdt_ops,
173 .flags = DM_FLAG_PRE_RELOC,