1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
10 #include <asm/utils.h>
12 #define DW_WDT_CR 0x00
13 #define DW_WDT_TORR 0x04
14 #define DW_WDT_CRR 0x0C
16 #define DW_WDT_CR_EN_OFFSET 0x00
17 #define DW_WDT_CR_RMOD_OFFSET 0x01
18 #define DW_WDT_CR_RMOD_VAL 0x00
19 #define DW_WDT_CRR_RESTART_VAL 0x76
21 struct designware_wdt_priv {
26 * Set the watchdog time interval.
29 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
34 /* calculate the timeout range value */
35 i = log_2_n_round_up(timeout * clk_khz) - 16;
38 writel(i | (i << 4), base + DW_WDT_TORR);
43 static void designware_wdt_enable(void __iomem *base)
45 writel((DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET) |
46 BIT(DW_WDT_CR_EN_OFFSET),
50 static unsigned int designware_wdt_is_enabled(void __iomem *base)
52 return readl(base + DW_WDT_CR) & BIT(0);
55 static void designware_wdt_reset_common(void __iomem *base)
57 if (designware_wdt_is_enabled(base))
58 /* restart the watchdog counter */
59 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
62 #if !CONFIG_IS_ENABLED(WDT)
63 void hw_watchdog_reset(void)
65 designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
68 void hw_watchdog_init(void)
70 /* reset to disable the watchdog */
72 /* set timer in miliseconds */
73 designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
74 CONFIG_DW_WDT_CLOCK_KHZ,
75 CONFIG_WATCHDOG_TIMEOUT_MSECS);
76 /* enable the watchdog */
77 designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
78 /* reset the watchdog */
82 static int designware_wdt_reset(struct udevice *dev)
84 struct designware_wdt_priv *priv = dev_get_priv(dev);
86 designware_wdt_reset_common(priv->base);
91 static int designware_wdt_stop(struct udevice *dev)
93 struct designware_wdt_priv *priv = dev_get_priv(dev);
95 designware_wdt_reset(dev);
96 writel(DW_WDT_CR_RMOD_VAL << DW_WDT_CR_RMOD_OFFSET,
97 priv->base + DW_WDT_CR);
102 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
104 struct designware_wdt_priv *priv = dev_get_priv(dev);
106 designware_wdt_stop(dev);
108 /* set timer in miliseconds */
109 designware_wdt_settimeout(priv->base, CONFIG_DW_WDT_CLOCK_KHZ, timeout);
111 designware_wdt_enable(priv->base);
113 /* reset the watchdog */
114 return designware_wdt_reset(dev);
117 static int designware_wdt_probe(struct udevice *dev)
119 struct designware_wdt_priv *priv = dev_get_priv(dev);
121 priv->base = dev_remap_addr(dev);
125 /* reset to disable the watchdog */
126 return designware_wdt_stop(dev);
129 static const struct wdt_ops designware_wdt_ops = {
130 .start = designware_wdt_start,
131 .reset = designware_wdt_reset,
132 .stop = designware_wdt_stop,
135 static const struct udevice_id designware_wdt_ids[] = {
136 { .compatible = "snps,dw-wdt"},
140 U_BOOT_DRIVER(designware_wdt) = {
141 .name = "designware_wdt",
143 .of_match = designware_wdt_ids,
144 .priv_auto_alloc_size = sizeof(struct designware_wdt_priv),
145 .probe = designware_wdt_probe,
146 .ops = &designware_wdt_ops,
147 .flags = DM_FLAG_PRE_RELOC,