1 // SPDX-License-Identifier: GPL-2.0+
3 * Marvell Armada 37xx SoC Watchdog Driver
5 * Marek Behun <marek.behun@nic.cz>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <dm/device_compat.h>
16 DECLARE_GLOBAL_DATA_PTR;
19 void __iomem *sel_reg;
26 * We use Counter 1 as watchdog timer, and Counter 0 for re-triggering Counter 1
29 #define CNTR_CTRL(id) ((id) * 0x10)
30 #define CNTR_CTRL_ENABLE 0x0001
31 #define CNTR_CTRL_ACTIVE 0x0002
32 #define CNTR_CTRL_MODE_MASK 0x000c
33 #define CNTR_CTRL_MODE_ONESHOT 0x0000
34 #define CNTR_CTRL_MODE_HWSIG 0x000c
35 #define CNTR_CTRL_TRIG_SRC_MASK 0x00f0
36 #define CNTR_CTRL_TRIG_SRC_PREV_CNTR 0x0050
37 #define CNTR_CTRL_PRESCALE_MASK 0xff00
38 #define CNTR_CTRL_PRESCALE_MIN 2
39 #define CNTR_CTRL_PRESCALE_SHIFT 8
41 #define CNTR_COUNT_LOW(id) (CNTR_CTRL(id) + 0x4)
42 #define CNTR_COUNT_HIGH(id) (CNTR_CTRL(id) + 0x8)
44 static void set_counter_value(struct a37xx_wdt *priv, int id, u64 val)
46 writel(val & 0xffffffff, priv->reg + CNTR_COUNT_LOW(id));
47 writel(val >> 32, priv->reg + CNTR_COUNT_HIGH(id));
50 static void counter_enable(struct a37xx_wdt *priv, int id)
52 setbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
55 static void counter_disable(struct a37xx_wdt *priv, int id)
57 clrbits_le32(priv->reg + CNTR_CTRL(id), CNTR_CTRL_ENABLE);
60 static int init_counter(struct a37xx_wdt *priv, int id, u32 mode, u32 trig_src)
64 reg = readl(priv->reg + CNTR_CTRL(id));
65 if (reg & CNTR_CTRL_ACTIVE)
68 reg &= ~(CNTR_CTRL_MODE_MASK | CNTR_CTRL_PRESCALE_MASK |
69 CNTR_CTRL_TRIG_SRC_MASK);
74 /* set prescaler to the min value */
75 reg |= CNTR_CTRL_PRESCALE_MIN << CNTR_CTRL_PRESCALE_SHIFT;
77 /* set trigger source */
80 writel(reg, priv->reg + CNTR_CTRL(id));
85 static int a37xx_wdt_reset(struct udevice *dev)
87 struct a37xx_wdt *priv = dev_get_priv(dev);
92 /* counter 1 is retriggered by forcing end count on counter 0 */
93 counter_disable(priv, 0);
94 counter_enable(priv, 0);
99 static int a37xx_wdt_expire_now(struct udevice *dev, ulong flags)
101 struct a37xx_wdt *priv = dev_get_priv(dev);
103 /* first we set timeout to 0 */
104 counter_disable(priv, 1);
105 set_counter_value(priv, 1, 0);
106 counter_enable(priv, 1);
108 /* and then we start counter 1 by forcing end count on counter 0 */
109 counter_disable(priv, 0);
110 counter_enable(priv, 0);
115 static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags)
117 struct a37xx_wdt *priv = dev_get_priv(dev);
120 err = init_counter(priv, 0, CNTR_CTRL_MODE_ONESHOT, 0);
124 err = init_counter(priv, 1, CNTR_CTRL_MODE_HWSIG,
125 CNTR_CTRL_TRIG_SRC_PREV_CNTR);
129 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN;
131 set_counter_value(priv, 0, 0);
132 set_counter_value(priv, 1, priv->timeout);
133 counter_enable(priv, 1);
135 /* we have to force end count on counter 0 to start counter 1 */
136 counter_enable(priv, 0);
141 static int a37xx_wdt_stop(struct udevice *dev)
143 struct a37xx_wdt *priv = dev_get_priv(dev);
145 counter_disable(priv, 1);
146 counter_disable(priv, 0);
147 writel(0, priv->sel_reg);
152 static int a37xx_wdt_probe(struct udevice *dev)
154 struct a37xx_wdt *priv = dev_get_priv(dev);
157 addr = dev_read_addr_index(dev, 0);
158 if (addr == FDT_ADDR_T_NONE)
160 priv->sel_reg = (void __iomem *)addr;
162 addr = dev_read_addr_index(dev, 1);
163 if (addr == FDT_ADDR_T_NONE)
165 priv->reg = (void __iomem *)addr;
167 priv->clk_rate = (ulong)get_ref_clk() * 1000000;
170 * We use counter 1 as watchdog timer, therefore we only set bit
171 * TIMER1_IS_WCHDOG_TIMER. Counter 0 is only used to force re-trigger on
174 writel(1 << 1, priv->sel_reg);
178 dev_err(dev, "no io address\n");
182 static const struct wdt_ops a37xx_wdt_ops = {
183 .start = a37xx_wdt_start,
184 .reset = a37xx_wdt_reset,
185 .stop = a37xx_wdt_stop,
186 .expire_now = a37xx_wdt_expire_now,
189 static const struct udevice_id a37xx_wdt_ids[] = {
190 { .compatible = "marvell,armada-3700-wdt" },
194 U_BOOT_DRIVER(a37xx_wdt) = {
195 .name = "armada_37xx_wdt",
197 .of_match = a37xx_wdt_ids,
198 .probe = a37xx_wdt_probe,
199 .priv_auto_alloc_size = sizeof(struct a37xx_wdt),
200 .ops = &a37xx_wdt_ops,