1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for one wire controller in some i.MX Socs
5 * There are currently two silicon variants:
6 * V1: i.MX21, i.MX27, i.MX31, i.MX51
7 * V2: i.MX25, i.MX35, i.MX50, i.MX53
8 * Newer i.MX SoCs such as the i.MX6 do not have one wire controllers.
10 * The V1 controller only supports single bit operations.
11 * The V2 controller is backwards compatible on the register level but adds
12 * byte size operations and a "search ROM accelerator mode"
14 * This driver does not currently support the search ROM accelerator
16 * Copyright (c) 2018 Flowbird
17 * Martin Fuzzey <martin.fuzzey@flowbird.group>
20 #include <asm/arch/clock.h>
23 #include <dm/device_compat.h>
29 #define MXC_W1_CONTROL_RPP BIT(7)
30 #define MXC_W1_CONTROL_PST BIT(6)
31 #define MXC_W1_CONTROL_WR(x) BIT(5 - (x))
32 #define MXC_W1_CONTROL_RDST BIT(3)
37 /* Registers below on V2 silicon only */
41 #define MXC_W1_INTERRUPT_TBE BIT(2)
42 #define MXC_W1_INTERRUPT_TSRE BIT(3)
43 #define MXC_W1_INTERRUPT_RBF BIT(4)
44 #define MXC_W1_INTERRUPT_RSRF BIT(5)
50 struct mxc_w1_regs *regs;
54 * this is the low level routine to read/write a bit on the One Wire
55 * interface on the hardware. It does write 0 if parameter bit is set
56 * to 0, otherwise a write 1/read.
58 static u8 mxc_w1_touch_bit(struct mxc_w1_pdata *pdata, u8 bit)
60 u16 *ctrl_addr = &pdata->regs->control;
61 u16 mask = MXC_W1_CONTROL_WR(bit);
62 unsigned int timeout_cnt = 400; /* Takes max. 120us according to
66 writew(mask, ctrl_addr);
68 while (timeout_cnt--) {
69 if (!(readw(ctrl_addr) & mask))
75 return (readw(ctrl_addr) & MXC_W1_CONTROL_RDST) ? 1 : 0;
78 static u8 mxc_w1_read_byte(struct udevice *dev)
80 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
81 struct mxc_w1_regs *regs = pdata->regs;
84 if (dev_get_driver_data(dev) < 2) {
88 for (i = 0; i < 8; i++)
89 ret |= (mxc_w1_touch_bit(pdata, 1) << i);
95 writew(0xFF, ®s->tx_rx);
98 udelay(1); /* Without this bytes are sometimes duplicated... */
99 status = readw(®s->interrupt);
100 } while (!(status & MXC_W1_INTERRUPT_RBF));
102 return (u8)readw(®s->tx_rx);
105 static void mxc_w1_write_byte(struct udevice *dev, u8 byte)
107 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
108 struct mxc_w1_regs *regs = pdata->regs;
111 if (dev_get_driver_data(dev) < 2) {
114 for (i = 0; i < 8; i++)
115 mxc_w1_touch_bit(pdata, (byte >> i) & 0x1);
121 writew(byte, ®s->tx_rx);
125 status = readw(®s->interrupt);
126 } while (!(status & MXC_W1_INTERRUPT_TSRE));
129 static bool mxc_w1_reset(struct udevice *dev)
131 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
134 writew(MXC_W1_CONTROL_RPP, &pdata->regs->control);
137 reg_val = readw(&pdata->regs->control);
138 } while (reg_val & MXC_W1_CONTROL_RPP);
140 return !(reg_val & MXC_W1_CONTROL_PST);
143 static u8 mxc_w1_triplet(struct udevice *dev, bool bdir)
145 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
146 u8 id_bit = mxc_w1_touch_bit(pdata, 1);
147 u8 comp_bit = mxc_w1_touch_bit(pdata, 1);
150 if (id_bit && comp_bit)
151 return 0x03; /* error */
153 if (!id_bit && !comp_bit) {
154 /* Both bits are valid, take the direction given */
155 retval = bdir ? 0x04 : 0;
157 /* Only one bit is valid, take that direction */
159 retval = id_bit ? 0x05 : 0x02;
162 mxc_w1_touch_bit(pdata, bdir);
167 static int mxc_w1_ofdata_to_platdata(struct udevice *dev)
169 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
172 addr = devfdt_get_addr(dev);
173 if (addr == FDT_ADDR_T_NONE)
176 pdata->regs = (struct mxc_w1_regs *)addr;
181 static int mxc_w1_probe(struct udevice *dev)
183 struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
184 unsigned int clkrate = mxc_get_clock(MXC_IPG_PERCLK);
187 if (clkrate < 10000000) {
188 dev_err(dev, "input clock frequency (%u Hz) too low\n",
193 clkdiv = clkrate / 1000000;
195 if (clkrate < 980000 || clkrate > 1020000) {
196 dev_err(dev, "Incorrect time base frequency %u Hz\n", clkrate);
200 writew(clkdiv - 1, &pdata->regs->time_divider);
205 static const struct w1_ops mxc_w1_ops = {
206 .read_byte = mxc_w1_read_byte,
207 .reset = mxc_w1_reset,
208 .triplet = mxc_w1_triplet,
209 .write_byte = mxc_w1_write_byte,
212 static const struct udevice_id mxc_w1_id[] = {
213 { .compatible = "fsl,imx21-owire", .data = 1 },
214 { .compatible = "fsl,imx27-owire", .data = 1 },
215 { .compatible = "fsl,imx31-owire", .data = 1 },
216 { .compatible = "fsl,imx51-owire", .data = 1 },
218 { .compatible = "fsl,imx25-owire", .data = 2 },
219 { .compatible = "fsl,imx35-owire", .data = 2 },
220 { .compatible = "fsl,imx50-owire", .data = 2 },
221 { .compatible = "fsl,imx53-owire", .data = 2 },
225 U_BOOT_DRIVER(mxc_w1_drv) = {
227 .name = "mxc_w1_drv",
228 .of_match = mxc_w1_id,
229 .ofdata_to_platdata = mxc_w1_ofdata_to_platdata,
231 .platdata_auto_alloc_size = sizeof(struct mxc_w1_pdata),
232 .probe = mxc_w1_probe,