2 * Copyright (c) 2011 The Chromium OS Authors.
3 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/system.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/funcmux.h>
16 #include <asm/arch/pinmux.h>
17 #include <asm/arch/pwm.h>
18 #include <asm/arch/display.h>
19 #include <asm/arch-tegra/timer.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 /* These are the stages we go throuh in enabling the LCD */
34 #define FDT_LCD_TIMINGS 4
37 FDT_LCD_TIMING_REF_TO_SYNC,
38 FDT_LCD_TIMING_SYNC_WIDTH,
39 FDT_LCD_TIMING_BACK_PORCH,
40 FDT_LCD_TIMING_FRONT_PORCH,
46 FDT_LCD_CACHE_OFF = 0,
47 FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0,
48 FDT_LCD_CACHE_WRITE_BACK = 1 << 1,
49 FDT_LCD_CACHE_FLUSH = 1 << 2,
50 FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK |
54 /* Information about the display controller */
55 struct tegra_lcd_priv {
56 enum stage_t stage; /* Current stage we are at */
57 unsigned long timer_next; /* Time we can move onto next stage */
58 int width; /* width in pixels */
59 int height; /* height in pixels */
62 * log2 of number of bpp, in general, unless it bpp is 24 in which
63 * case this field holds 24 also! This is a U-Boot thing.
66 struct disp_ctlr *disp; /* Display controller to use */
67 fdt_addr_t frame_buffer; /* Address of frame buffer */
68 unsigned pixel_clock; /* Pixel clock in Hz */
69 uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */
70 uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */
71 int pwm_channel; /* PWM channel to use for backlight */
72 enum lcd_cache_t cache_type;
74 struct gpio_desc backlight_en; /* GPIO for backlight enable */
75 struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
76 struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
77 struct gpio_desc panel_vdd; /* GPIO for panel vdd */
79 * Panel required timings
80 * Timing 1: delay between panel_vdd-rise and data-rise
81 * Timing 2: delay between data-rise and backlight_vdd-rise
82 * Timing 3: delay between backlight_vdd and pwm-rise
83 * Timing 4: delay between pwm-rise and backlight_en-rise
85 uint panel_timings[FDT_LCD_TIMINGS];
89 /* Maximum LCD size we support */
92 LCD_MAX_LOG2_BPP = VIDEO_BPP16,
95 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
97 unsigned h_dda, v_dda;
100 val = readl(&dc->cmd.disp_win_header);
101 val |= WINDOW_A_SELECT;
102 writel(val, &dc->cmd.disp_win_header);
104 writel(win->fmt, &dc->win.color_depth);
106 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
107 BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
109 val = win->out_x << H_POSITION_SHIFT;
110 val |= win->out_y << V_POSITION_SHIFT;
111 writel(val, &dc->win.pos);
113 val = win->out_w << H_SIZE_SHIFT;
114 val |= win->out_h << V_SIZE_SHIFT;
115 writel(val, &dc->win.size);
117 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
118 val |= win->h << V_PRESCALED_SIZE_SHIFT;
119 writel(val, &dc->win.prescaled_size);
121 writel(0, &dc->win.h_initial_dda);
122 writel(0, &dc->win.v_initial_dda);
124 h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
125 v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
127 val = h_dda << H_DDA_INC_SHIFT;
128 val |= v_dda << V_DDA_INC_SHIFT;
129 writel(val, &dc->win.dda_increment);
131 writel(win->stride, &dc->win.line_stride);
132 writel(0, &dc->win.buf_stride);
137 writel(val, &dc->win.win_opt);
139 writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
140 writel(win->x, &dc->winbuf.addr_h_offset);
141 writel(win->y, &dc->winbuf.addr_v_offset);
143 writel(0xff00, &dc->win.blend_nokey);
144 writel(0xff00, &dc->win.blend_1win);
146 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
147 val |= GENERAL_UPDATE | WIN_A_UPDATE;
148 writel(val, &dc->cmd.state_ctrl);
151 static void write_pair(struct tegra_lcd_priv *priv, int item, u32 *reg)
153 writel(priv->horiz_timing[item] |
154 (priv->vert_timing[item] << 16), reg);
157 static int update_display_mode(struct dc_disp_reg *disp,
158 struct tegra_lcd_priv *priv)
164 writel(0x0, &disp->disp_timing_opt);
165 write_pair(priv, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
166 write_pair(priv, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
167 write_pair(priv, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
168 write_pair(priv, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
170 writel(priv->width | (priv->height << 16), &disp->disp_active);
172 val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
173 val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
174 writel(val, &disp->data_enable_opt);
176 val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
177 val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
178 val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
179 writel(val, &disp->disp_interface_ctrl);
182 * The pixel clock divider is in 7.1 format (where the bottom bit
183 * represents 0.5). Here we calculate the divider needed to get from
184 * the display clock (typically 600MHz) to the pixel clock. We round
185 * up or down as requried.
187 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
188 div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
189 debug("Display clock %lu, divider %lu\n", rate, div);
191 writel(0x00010001, &disp->shift_clk_opt);
193 val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
194 val |= div << SHIFT_CLK_DIVIDER_SHIFT;
195 writel(val, &disp->disp_clk_ctrl);
200 /* Start up the display and turn on power to PWMs */
201 static void basic_init(struct dc_cmd_reg *cmd)
205 writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
206 writel(0x0000011a, &cmd->cont_syncpt_vsync);
207 writel(0x00000000, &cmd->int_type);
208 writel(0x00000000, &cmd->int_polarity);
209 writel(0x00000000, &cmd->int_mask);
210 writel(0x00000000, &cmd->int_enb);
212 val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
213 val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
215 writel(val, &cmd->disp_pow_ctrl);
217 val = readl(&cmd->disp_cmd);
218 val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
219 writel(val, &cmd->disp_cmd);
222 static void basic_init_timer(struct dc_disp_reg *disp)
224 writel(0x00000020, &disp->mem_high_pri);
225 writel(0x00000001, &disp->mem_high_pri_timer);
228 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
235 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
242 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
249 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
259 static void rgb_enable(struct dc_com_reg *com)
263 for (i = 0; i < PIN_REG_COUNT; i++) {
264 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
265 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
266 writel(rgb_data_tab[i], &com->pin_output_data[i]);
269 for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
270 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
273 static int setup_window(struct disp_ctl_win *win,
274 struct tegra_lcd_priv *priv)
278 win->w = priv->width;
279 win->h = priv->height;
282 win->out_w = priv->width;
283 win->out_h = priv->height;
284 win->phys_addr = priv->frame_buffer;
285 win->stride = priv->width * (1 << priv->log2_bpp) / 8;
286 debug("%s: depth = %d\n", __func__, priv->log2_bpp);
287 switch (priv->log2_bpp) {
290 win->fmt = COLOR_DEPTH_R8G8B8A8;
294 win->fmt = COLOR_DEPTH_B5G6R5;
299 debug("Unsupported LCD bit depth");
306 static void debug_timing(const char *name, unsigned int timing[])
311 debug("%s timing: ", name);
312 for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
313 debug("%d ", timing[i]);
319 * Register a new display based on device tree configuration.
321 * The frame buffer can be positioned by U-Boot or overriden by the fdt.
322 * You should pass in the U-Boot address here, and check the contents of
323 * struct tegra_lcd_priv to see what was actually chosen.
325 * @param blob Device tree blob
326 * @param priv Driver's private data
327 * @param default_lcd_base Default address of LCD frame buffer
328 * @return 0 if ok, -1 on error (unsupported bits per pixel)
330 static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
331 void *default_lcd_base)
333 struct disp_ctl_win window;
336 priv->frame_buffer = (u32)default_lcd_base;
338 dc = (struct dc_ctlr *)priv->disp;
341 * A header file for clock constants was NAKed upstream.
342 * TODO: Put this into the FDT and fdt_lcd struct when we have clock
345 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
347 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
349 basic_init(&dc->cmd);
350 basic_init_timer(&dc->disp);
351 rgb_enable(&dc->com);
353 if (priv->pixel_clock)
354 update_display_mode(&dc->disp, priv);
356 if (setup_window(&window, priv))
359 update_window(dc, &window);
365 * Handle the next stage of device init
367 static int handle_stage(const void *blob, struct tegra_lcd_priv *priv)
369 debug("%s: stage %d\n", __func__, priv->stage);
371 /* do the things for this stage */
372 switch (priv->stage) {
375 * It is possible that the FDT has requested that the LCD be
376 * disabled. We currently don't support this. It would require
377 * changes to U-Boot LCD subsystem to have LCD support
378 * compiled in but not used. An easier option might be to
379 * still have a frame buffer, but leave the backlight off and
380 * remove all mention of lcd in the stdout environment
384 funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
386 case STAGE_PANEL_VDD:
387 if (dm_gpio_is_valid(&priv->panel_vdd))
388 dm_gpio_set_value(&priv->panel_vdd, 1);
391 if (dm_gpio_is_valid(&priv->lvds_shutdown))
392 dm_gpio_set_value(&priv->lvds_shutdown, 1);
394 case STAGE_BACKLIGHT_VDD:
395 if (dm_gpio_is_valid(&priv->backlight_vdd))
396 dm_gpio_set_value(&priv->backlight_vdd, 1);
399 /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
400 pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
401 pinmux_tristate_disable(PMUX_PINGRP_GPU);
403 pwm_enable(priv->pwm_channel, 32768, 0xdf, 1);
405 case STAGE_BACKLIGHT_EN:
406 if (dm_gpio_is_valid(&priv->backlight_en))
407 dm_gpio_set_value(&priv->backlight_en, 1);
413 /* set up timer for next stage */
414 priv->timer_next = timer_get_us();
415 if (priv->stage < FDT_LCD_TIMINGS)
416 priv->timer_next += priv->panel_timings[priv->stage] * 1000;
418 /* move to next stage */
424 * Perform the next stage of the LCD init if it is time to do so.
426 * LCD init can be time-consuming because of the number of delays we need
427 * while waiting for the backlight power supply, etc. This function can
428 * be called at various times during U-Boot operation to advance the
429 * initialization of the LCD to the next stage if sufficient time has
430 * passed since the last stage. It keeps track of what stage it is up to
431 * and the time that it is permitted to move to the next stage.
433 * The final call should have wait=1 to complete the init.
435 * @param blob fdt blob containing LCD information
436 * @param wait 1 to wait until all init is complete, and then return
437 * 0 to return immediately, potentially doing nothing if it is
438 * not yet time for the next init.
440 static int tegra_lcd_check_next_stage(const void *blob,
441 struct tegra_lcd_priv *priv, int wait)
443 if (priv->stage == STAGE_DONE)
447 /* wait if we need to */
448 debug("%s: stage %d\n", __func__, priv->stage);
449 if (priv->stage != STAGE_START) {
450 int delay = priv->timer_next - timer_get_us();
460 if (handle_stage(blob, priv))
462 } while (wait && priv->stage != STAGE_DONE);
463 if (priv->stage == STAGE_DONE)
464 debug("%s: LCD init complete\n", __func__);
469 static int tegra_lcd_probe(struct udevice *dev)
471 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
472 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
473 struct tegra_lcd_priv *priv = dev_get_priv(dev);
474 const void *blob = gd->fdt_blob;
475 int type = DCACHE_OFF;
477 /* Initialize the Tegra display controller */
478 if (tegra_display_probe(blob, priv, (void *)plat->base)) {
479 printf("%s: Failed to probe display driver\n", __func__);
483 tegra_lcd_check_next_stage(blob, priv, 1);
485 /* Set up the LCD caching as requested */
486 if (priv->cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
487 type = DCACHE_WRITETHROUGH;
488 else if (priv->cache_type & FDT_LCD_CACHE_WRITE_BACK)
489 type = DCACHE_WRITEBACK;
490 mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size, type);
492 /* Enable flushing after LCD writes if requested */
493 video_set_flush_dcache(dev, priv->cache_type & FDT_LCD_CACHE_FLUSH);
495 uc_priv->xsize = priv->width;
496 uc_priv->ysize = priv->height;
497 uc_priv->bpix = priv->log2_bpp;
498 debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
504 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
506 struct tegra_lcd_priv *priv = dev_get_priv(dev);
507 const void *blob = gd->fdt_blob;
508 int node = dev->of_offset;
509 int front, back, ref;
514 priv->disp = (struct disp_ctlr *)dev_get_addr(dev);
516 debug("%s: No display controller address\n", __func__);
520 rgb = fdt_subnode_offset(blob, node, "rgb");
522 panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
523 if (panel_node < 0) {
524 debug("%s: Cannot find panel information\n", __func__);
528 priv->width = fdtdec_get_int(blob, panel_node, "xres", -1);
529 priv->height = fdtdec_get_int(blob, panel_node, "yres", -1);
530 priv->pixel_clock = fdtdec_get_int(blob, panel_node, "clock", 0);
531 if (!priv->pixel_clock || priv->width == -1 || priv->height == -1) {
532 debug("%s: Pixel parameters missing\n", __func__);
536 back = fdtdec_get_int(blob, panel_node, "left-margin", -1);
537 front = fdtdec_get_int(blob, panel_node, "right-margin", -1);
538 ref = fdtdec_get_int(blob, panel_node, "hsync-len", -1);
539 if ((back | front | ref) == -1) {
540 debug("%s: Horizontal parameters missing\n", __func__);
544 /* Use a ref-to-sync of 1 always, and take this from the front porch */
545 priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
546 priv->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
547 priv->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
548 priv->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
549 priv->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
550 debug_timing("horiz", priv->horiz_timing);
552 back = fdtdec_get_int(blob, panel_node, "upper-margin", -1);
553 front = fdtdec_get_int(blob, panel_node, "lower-margin", -1);
554 ref = fdtdec_get_int(blob, panel_node, "vsync-len", -1);
555 if ((back | front | ref) == -1) {
556 debug("%s: Vertical parameters missing\n", __func__);
560 priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
561 priv->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
562 priv->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
563 priv->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
564 priv->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
565 debug_timing("vert", priv->vert_timing);
567 bpp = fdtdec_get_int(blob, panel_node, "nvidia,bits-per-pixel", -1);
569 if (bpp == (1 << bit))
570 priv->log2_bpp = bit;
572 priv->log2_bpp = bpp;
574 debug("%s: Pixel bpp parameters missing\n", __func__);
578 priv->pwm_channel = pwm_request(blob, panel_node, "nvidia,pwm");
579 if (priv->pwm_channel < 0) {
580 debug("%s: Unable to request PWM channel\n", __func__);
584 priv->cache_type = fdtdec_get_int(blob, panel_node, "nvidia,cache-type",
585 FDT_LCD_CACHE_WRITE_BACK_FLUSH);
587 /* These GPIOs are all optional */
588 gpio_request_by_name_nodev(blob, panel_node,
589 "nvidia,backlight-enable-gpios", 0,
590 &priv->backlight_en, GPIOD_IS_OUT);
591 gpio_request_by_name_nodev(blob, panel_node,
592 "nvidia,lvds-shutdown-gpios", 0,
593 &priv->lvds_shutdown, GPIOD_IS_OUT);
594 gpio_request_by_name_nodev(blob, panel_node,
595 "nvidia,backlight-vdd-gpios", 0,
596 &priv->backlight_vdd, GPIOD_IS_OUT);
597 gpio_request_by_name_nodev(blob, panel_node,
598 "nvidia,panel-vdd-gpios", 0,
599 &priv->panel_vdd, GPIOD_IS_OUT);
601 if (fdtdec_get_int_array(blob, panel_node, "nvidia,panel-timings",
602 priv->panel_timings, FDT_LCD_TIMINGS))
608 static int tegra_lcd_bind(struct udevice *dev)
610 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
612 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
613 (1 << LCD_MAX_LOG2_BPP) / 8;
618 static const struct video_ops tegra_lcd_ops = {
621 static const struct udevice_id tegra_lcd_ids[] = {
622 { .compatible = "nvidia,tegra20-dc" },
626 U_BOOT_DRIVER(tegra_lcd) = {
629 .of_match = tegra_lcd_ids,
630 .ops = &tegra_lcd_ops,
631 .bind = tegra_lcd_bind,
632 .probe = tegra_lcd_probe,
633 .ofdata_to_platdata = tegra_lcd_ofdata_to_platdata,
634 .priv_auto_alloc_size = sizeof(struct tegra_lcd_priv),