drivers/video/tegra.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <fdtdec.h>
   9 #include <panel.h>
  10 #include <part.h>
  11 #include <pwm.h>
  12 #include <video.h>
  13 #include <asm/cache.h>
  14 #include <asm/system.h>
  15 #include <asm/gpio.h>
  16 #include <asm/io.h>
  17
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/funcmux.h>
  20 #include <asm/arch/pinmux.h>
  21 #include <asm/arch/pwm.h>
  22 #include <asm/arch/display.h>
  23 #include <asm/arch-tegra/timer.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* Information about the display controller */
  28 struct tegra_lcd_priv {
  29         int width;                      /* width in pixels */
  30         int height;                     /* height in pixels */
  31         enum video_log2_bpp log2_bpp;   /* colour depth */
  32         struct display_timing timing;
  33         struct udevice *panel;
  34         struct disp_ctlr *disp;         /* Display controller to use */
  35         fdt_addr_t frame_buffer;        /* Address of frame buffer */
  36         unsigned pixel_clock;           /* Pixel clock in Hz */
  37 };
  38
  39 enum {
  40         /* Maximum LCD size we support */
  41         LCD_MAX_WIDTH           = 1366,
  42         LCD_MAX_HEIGHT          = 768,
  43         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  44 };
  45
  46 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  47 {
  48         unsigned h_dda, v_dda;
  49         unsigned long val;
  50
  51         val = readl(&dc->cmd.disp_win_header);
  52         val |= WINDOW_A_SELECT;
  53         writel(val, &dc->cmd.disp_win_header);
  54
  55         writel(win->fmt, &dc->win.color_depth);
  56
  57         clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  58                         BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  59
  60         val = win->out_x << H_POSITION_SHIFT;
  61         val |= win->out_y << V_POSITION_SHIFT;
  62         writel(val, &dc->win.pos);
  63
  64         val = win->out_w << H_SIZE_SHIFT;
  65         val |= win->out_h << V_SIZE_SHIFT;
  66         writel(val, &dc->win.size);
  67
  68         val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  69         val |= win->h << V_PRESCALED_SIZE_SHIFT;
  70         writel(val, &dc->win.prescaled_size);
  71
  72         writel(0, &dc->win.h_initial_dda);
  73         writel(0, &dc->win.v_initial_dda);
  74
  75         h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  76         v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  77
  78         val = h_dda << H_DDA_INC_SHIFT;
  79         val |= v_dda << V_DDA_INC_SHIFT;
  80         writel(val, &dc->win.dda_increment);
  81
  82         writel(win->stride, &dc->win.line_stride);
  83         writel(0, &dc->win.buf_stride);
  84
  85         val = WIN_ENABLE;
  86         if (win->bpp < 24)
  87                 val |= COLOR_EXPAND;
  88         writel(val, &dc->win.win_opt);
  89
  90         writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  91         writel(win->x, &dc->winbuf.addr_h_offset);
  92         writel(win->y, &dc->winbuf.addr_v_offset);
  93
  94         writel(0xff00, &dc->win.blend_nokey);
  95         writel(0xff00, &dc->win.blend_1win);
  96
  97         val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  98         val |= GENERAL_UPDATE | WIN_A_UPDATE;
  99         writel(val, &dc->cmd.state_ctrl);
 100 }
 101
 102 static int update_display_mode(struct dc_disp_reg *disp,
 103                                struct tegra_lcd_priv *priv)
 104 {
 105         struct display_timing *dt = &priv->timing;
 106         unsigned long val;
 107         unsigned long rate;
 108         unsigned long div;
 109
 110         writel(0x0, &disp->disp_timing_opt);
 111
 112         writel(1 | 1 << 16, &disp->ref_to_sync);
 113         writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
 114         writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
 115                &disp->back_porch);
 116         writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
 117                &disp->front_porch);
 118         writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
 119
 120         val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
 121         val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
 122         writel(val, &disp->data_enable_opt);
 123
 124         val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
 125         val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
 126         val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
 127         writel(val, &disp->disp_interface_ctrl);
 128
 129         /*
 130          * The pixel clock divider is in 7.1 format (where the bottom bit
 131          * represents 0.5). Here we calculate the divider needed to get from
 132          * the display clock (typically 600MHz) to the pixel clock. We round
 133          * up or down as requried.
 134          */
 135         rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
 136         div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
 137         debug("Display clock %lu, divider %lu\n", rate, div);
 138
 139         writel(0x00010001, &disp->shift_clk_opt);
 140
 141         val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
 142         val |= div << SHIFT_CLK_DIVIDER_SHIFT;
 143         writel(val, &disp->disp_clk_ctrl);
 144
 145         return 0;
 146 }
 147
 148 /* Start up the display and turn on power to PWMs */
 149 static void basic_init(struct dc_cmd_reg *cmd)
 150 {
 151         u32 val;
 152
 153         writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
 154         writel(0x0000011a, &cmd->cont_syncpt_vsync);
 155         writel(0x00000000, &cmd->int_type);
 156         writel(0x00000000, &cmd->int_polarity);
 157         writel(0x00000000, &cmd->int_mask);
 158         writel(0x00000000, &cmd->int_enb);
 159
 160         val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
 161         val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
 162         val |= PM1_ENABLE;
 163         writel(val, &cmd->disp_pow_ctrl);
 164
 165         val = readl(&cmd->disp_cmd);
 166         val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
 167         writel(val, &cmd->disp_cmd);
 168 }
 169
 170 static void basic_init_timer(struct dc_disp_reg *disp)
 171 {
 172         writel(0x00000020, &disp->mem_high_pri);
 173         writel(0x00000001, &disp->mem_high_pri_timer);
 174 }
 175
 176 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
 177         0x00000000,
 178         0x00000000,
 179         0x00000000,
 180         0x00000000,
 181 };
 182
 183 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
 184         0x00000000,
 185         0x01000000,
 186         0x00000000,
 187         0x00000000,
 188 };
 189
 190 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
 191         0x00000000,
 192         0x00000000,
 193         0x00000000,
 194         0x00000000,
 195 };
 196
 197 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
 198         0x00000000,
 199         0x00000000,
 200         0x00000000,
 201         0x00000000,
 202         0x00210222,
 203         0x00002200,
 204         0x00020000,
 205 };
 206
 207 static void rgb_enable(struct dc_com_reg *com)
 208 {
 209         int i;
 210
 211         for (i = 0; i < PIN_REG_COUNT; i++) {
 212                 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
 213                 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
 214                 writel(rgb_data_tab[i], &com->pin_output_data[i]);
 215         }
 216
 217         for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
 218                 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
 219 }
 220
 221 static int setup_window(struct disp_ctl_win *win,
 222                         struct tegra_lcd_priv *priv)
 223 {
 224         win->x = 0;
 225         win->y = 0;
 226         win->w = priv->width;
 227         win->h = priv->height;
 228         win->out_x = 0;
 229         win->out_y = 0;
 230         win->out_w = priv->width;
 231         win->out_h = priv->height;
 232         win->phys_addr = priv->frame_buffer;
 233         win->stride = priv->width * (1 << priv->log2_bpp) / 8;
 234         debug("%s: depth = %d\n", __func__, priv->log2_bpp);
 235         switch (priv->log2_bpp) {
 236         case VIDEO_BPP32:
 237                 win->fmt = COLOR_DEPTH_R8G8B8A8;
 238                 win->bpp = 32;
 239                 break;
 240         case VIDEO_BPP16:
 241                 win->fmt = COLOR_DEPTH_B5G6R5;
 242                 win->bpp = 16;
 243                 break;
 244
 245         default:
 246                 debug("Unsupported LCD bit depth");
 247                 return -1;
 248         }
 249
 250         return 0;
 251 }
 252
 253 /**
 254  * Register a new display based on device tree configuration.
 255  *
 256  * The frame buffer can be positioned by U-Boot or overridden by the fdt.
 257  * You should pass in the U-Boot address here, and check the contents of
 258  * struct tegra_lcd_priv to see what was actually chosen.
 259  *
 260  * @param blob                  Device tree blob
 261  * @param priv                  Driver's private data
 262  * @param default_lcd_base      Default address of LCD frame buffer
 263  * @return 0 if ok, -1 on error (unsupported bits per pixel)
 264  */
 265 static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
 266                                void *default_lcd_base)
 267 {
 268         struct disp_ctl_win window;
 269         struct dc_ctlr *dc;
 270
 271         priv->frame_buffer = (u32)default_lcd_base;
 272
 273         dc = (struct dc_ctlr *)priv->disp;
 274
 275         /*
 276          * A header file for clock constants was NAKed upstream.
 277          * TODO: Put this into the FDT and fdt_lcd struct when we have clock
 278          * support there
 279          */
 280         clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
 281                                144 * 1000000);
 282         clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
 283                                600 * 1000000);
 284         basic_init(&dc->cmd);
 285         basic_init_timer(&dc->disp);
 286         rgb_enable(&dc->com);
 287
 288         if (priv->pixel_clock)
 289                 update_display_mode(&dc->disp, priv);
 290
 291         if (setup_window(&window, priv))
 292                 return -1;
 293
 294         update_window(dc, &window);
 295
 296         return 0;
 297 }
 298
 299 static int tegra_lcd_probe(struct udevice *dev)
 300 {
 301         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 302         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 303         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 304         const void *blob = gd->fdt_blob;
 305         int ret;
 306
 307         /* Initialize the Tegra display controller */
 308         funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
 309         if (tegra_display_probe(blob, priv, (void *)plat->base)) {
 310                 printf("%s: Failed to probe display driver\n", __func__);
 311                 return -1;
 312         }
 313
 314         pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
 315         pinmux_tristate_disable(PMUX_PINGRP_GPU);
 316
 317         ret = panel_enable_backlight(priv->panel);
 318         if (ret) {
 319                 debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
 320                 return ret;
 321         }
 322
 323         mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
 324                                         DCACHE_WRITETHROUGH);
 325
 326         /* Enable flushing after LCD writes if requested */
 327         video_set_flush_dcache(dev, true);
 328
 329         uc_priv->xsize = priv->width;
 330         uc_priv->ysize = priv->height;
 331         uc_priv->bpix = priv->log2_bpp;
 332         debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
 333               plat->size);
 334
 335         return 0;
 336 }
 337
 338 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 339 {
 340         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 341         const void *blob = gd->fdt_blob;
 342         struct display_timing *timing;
 343         int node = dev_of_offset(dev);
 344         int panel_node;
 345         int rgb;
 346         int ret;
 347
 348         priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
 349         if (!priv->disp) {
 350                 debug("%s: No display controller address\n", __func__);
 351                 return -EINVAL;
 352         }
 353
 354         rgb = fdt_subnode_offset(blob, node, "rgb");
 355         if (rgb < 0) {
 356                 debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
 357                       __func__, dev->name, rgb);
 358                 return -EINVAL;
 359         }
 360
 361         ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
 362         if (ret) {
 363                 debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
 364                       __func__, dev->name, ret);
 365                 return -EINVAL;
 366         }
 367         timing = &priv->timing;
 368         priv->width = timing->hactive.typ;
 369         priv->height = timing->vactive.typ;
 370         priv->pixel_clock = timing->pixelclock.typ;
 371         priv->log2_bpp = VIDEO_BPP16;
 372
 373         /*
 374          * Sadly the panel phandle is in an rgb subnode so we cannot use
 375          * uclass_get_device_by_phandle().
 376          */
 377         panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
 378         if (panel_node < 0) {
 379                 debug("%s: Cannot find panel information\n", __func__);
 380                 return -EINVAL;
 381         }
 382         ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
 383                                              &priv->panel);
 384         if (ret) {
 385                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
 386                       dev->name, ret);
 387                 return ret;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int tegra_lcd_bind(struct udevice *dev)
 394 {
 395         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 396         const void *blob = gd->fdt_blob;
 397         int node = dev_of_offset(dev);
 398         int rgb;
 399
 400         rgb = fdt_subnode_offset(blob, node, "rgb");
 401         if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
 402                 return -ENODEV;
 403
 404         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 405                 (1 << LCD_MAX_LOG2_BPP) / 8;
 406
 407         return 0;
 408 }
 409
 410 static const struct video_ops tegra_lcd_ops = {
 411 };
 412
 413 static const struct udevice_id tegra_lcd_ids[] = {
 414         { .compatible = "nvidia,tegra20-dc" },
 415         { }
 416 };
 417
 418 U_BOOT_DRIVER(tegra_lcd) = {
 419         .name   = "tegra_lcd",
 420         .id     = UCLASS_VIDEO,
 421         .of_match = tegra_lcd_ids,
 422         .ops    = &tegra_lcd_ops,
 423         .bind   = tegra_lcd_bind,
 424         .probe  = tegra_lcd_probe,
 425         .ofdata_to_platdata     = tegra_lcd_ofdata_to_platdata,
 426         .priv_auto_alloc_size   = sizeof(struct tegra_lcd_priv),
 427 };