drivers/video/tegra.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2011 The Chromium OS Authors.
   4  */
   5
   6 #include <common.h>
   7 #include <dm.h>
   8 #include <fdtdec.h>
   9 #include <panel.h>
  10 #include <pwm.h>
  11 #include <video.h>
  12 #include <asm/cache.h>
  13 #include <asm/system.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/funcmux.h>
  19 #include <asm/arch/pinmux.h>
  20 #include <asm/arch/pwm.h>
  21 #include <asm/arch/display.h>
  22 #include <asm/arch-tegra/timer.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* Information about the display controller */
  27 struct tegra_lcd_priv {
  28         int width;                      /* width in pixels */
  29         int height;                     /* height in pixels */
  30         enum video_log2_bpp log2_bpp;   /* colour depth */
  31         struct display_timing timing;
  32         struct udevice *panel;
  33         struct disp_ctlr *disp;         /* Display controller to use */
  34         fdt_addr_t frame_buffer;        /* Address of frame buffer */
  35         unsigned pixel_clock;           /* Pixel clock in Hz */
  36 };
  37
  38 enum {
  39         /* Maximum LCD size we support */
  40         LCD_MAX_WIDTH           = 1366,
  41         LCD_MAX_HEIGHT          = 768,
  42         LCD_MAX_LOG2_BPP        = VIDEO_BPP16,
  43 };
  44
  45 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
  46 {
  47         unsigned h_dda, v_dda;
  48         unsigned long val;
  49
  50         val = readl(&dc->cmd.disp_win_header);
  51         val |= WINDOW_A_SELECT;
  52         writel(val, &dc->cmd.disp_win_header);
  53
  54         writel(win->fmt, &dc->win.color_depth);
  55
  56         clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
  57                         BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
  58
  59         val = win->out_x << H_POSITION_SHIFT;
  60         val |= win->out_y << V_POSITION_SHIFT;
  61         writel(val, &dc->win.pos);
  62
  63         val = win->out_w << H_SIZE_SHIFT;
  64         val |= win->out_h << V_SIZE_SHIFT;
  65         writel(val, &dc->win.size);
  66
  67         val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
  68         val |= win->h << V_PRESCALED_SIZE_SHIFT;
  69         writel(val, &dc->win.prescaled_size);
  70
  71         writel(0, &dc->win.h_initial_dda);
  72         writel(0, &dc->win.v_initial_dda);
  73
  74         h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
  75         v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
  76
  77         val = h_dda << H_DDA_INC_SHIFT;
  78         val |= v_dda << V_DDA_INC_SHIFT;
  79         writel(val, &dc->win.dda_increment);
  80
  81         writel(win->stride, &dc->win.line_stride);
  82         writel(0, &dc->win.buf_stride);
  83
  84         val = WIN_ENABLE;
  85         if (win->bpp < 24)
  86                 val |= COLOR_EXPAND;
  87         writel(val, &dc->win.win_opt);
  88
  89         writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
  90         writel(win->x, &dc->winbuf.addr_h_offset);
  91         writel(win->y, &dc->winbuf.addr_v_offset);
  92
  93         writel(0xff00, &dc->win.blend_nokey);
  94         writel(0xff00, &dc->win.blend_1win);
  95
  96         val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
  97         val |= GENERAL_UPDATE | WIN_A_UPDATE;
  98         writel(val, &dc->cmd.state_ctrl);
  99 }
 100
 101 static int update_display_mode(struct dc_disp_reg *disp,
 102                                struct tegra_lcd_priv *priv)
 103 {
 104         struct display_timing *dt = &priv->timing;
 105         unsigned long val;
 106         unsigned long rate;
 107         unsigned long div;
 108
 109         writel(0x0, &disp->disp_timing_opt);
 110
 111         writel(1 | 1 << 16, &disp->ref_to_sync);
 112         writel(dt->hsync_len.typ | dt->vsync_len.typ << 16, &disp->sync_width);
 113         writel(dt->hback_porch.typ | dt->vback_porch.typ << 16,
 114                &disp->back_porch);
 115         writel((dt->hfront_porch.typ - 1) | (dt->vfront_porch.typ - 1) << 16,
 116                &disp->front_porch);
 117         writel(dt->hactive.typ | (dt->vactive.typ << 16), &disp->disp_active);
 118
 119         val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
 120         val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
 121         writel(val, &disp->data_enable_opt);
 122
 123         val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
 124         val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
 125         val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
 126         writel(val, &disp->disp_interface_ctrl);
 127
 128         /*
 129          * The pixel clock divider is in 7.1 format (where the bottom bit
 130          * represents 0.5). Here we calculate the divider needed to get from
 131          * the display clock (typically 600MHz) to the pixel clock. We round
 132          * up or down as requried.
 133          */
 134         rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
 135         div = ((rate * 2 + priv->pixel_clock / 2) / priv->pixel_clock) - 2;
 136         debug("Display clock %lu, divider %lu\n", rate, div);
 137
 138         writel(0x00010001, &disp->shift_clk_opt);
 139
 140         val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
 141         val |= div << SHIFT_CLK_DIVIDER_SHIFT;
 142         writel(val, &disp->disp_clk_ctrl);
 143
 144         return 0;
 145 }
 146
 147 /* Start up the display and turn on power to PWMs */
 148 static void basic_init(struct dc_cmd_reg *cmd)
 149 {
 150         u32 val;
 151
 152         writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
 153         writel(0x0000011a, &cmd->cont_syncpt_vsync);
 154         writel(0x00000000, &cmd->int_type);
 155         writel(0x00000000, &cmd->int_polarity);
 156         writel(0x00000000, &cmd->int_mask);
 157         writel(0x00000000, &cmd->int_enb);
 158
 159         val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
 160         val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
 161         val |= PM1_ENABLE;
 162         writel(val, &cmd->disp_pow_ctrl);
 163
 164         val = readl(&cmd->disp_cmd);
 165         val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
 166         writel(val, &cmd->disp_cmd);
 167 }
 168
 169 static void basic_init_timer(struct dc_disp_reg *disp)
 170 {
 171         writel(0x00000020, &disp->mem_high_pri);
 172         writel(0x00000001, &disp->mem_high_pri_timer);
 173 }
 174
 175 static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
 176         0x00000000,
 177         0x00000000,
 178         0x00000000,
 179         0x00000000,
 180 };
 181
 182 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
 183         0x00000000,
 184         0x01000000,
 185         0x00000000,
 186         0x00000000,
 187 };
 188
 189 static const u32 rgb_data_tab[PIN_REG_COUNT] = {
 190         0x00000000,
 191         0x00000000,
 192         0x00000000,
 193         0x00000000,
 194 };
 195
 196 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
 197         0x00000000,
 198         0x00000000,
 199         0x00000000,
 200         0x00000000,
 201         0x00210222,
 202         0x00002200,
 203         0x00020000,
 204 };
 205
 206 static void rgb_enable(struct dc_com_reg *com)
 207 {
 208         int i;
 209
 210         for (i = 0; i < PIN_REG_COUNT; i++) {
 211                 writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
 212                 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
 213                 writel(rgb_data_tab[i], &com->pin_output_data[i]);
 214         }
 215
 216         for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
 217                 writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
 218 }
 219
 220 static int setup_window(struct disp_ctl_win *win,
 221                         struct tegra_lcd_priv *priv)
 222 {
 223         win->x = 0;
 224         win->y = 0;
 225         win->w = priv->width;
 226         win->h = priv->height;
 227         win->out_x = 0;
 228         win->out_y = 0;
 229         win->out_w = priv->width;
 230         win->out_h = priv->height;
 231         win->phys_addr = priv->frame_buffer;
 232         win->stride = priv->width * (1 << priv->log2_bpp) / 8;
 233         debug("%s: depth = %d\n", __func__, priv->log2_bpp);
 234         switch (priv->log2_bpp) {
 235         case VIDEO_BPP32:
 236                 win->fmt = COLOR_DEPTH_R8G8B8A8;
 237                 win->bpp = 32;
 238                 break;
 239         case VIDEO_BPP16:
 240                 win->fmt = COLOR_DEPTH_B5G6R5;
 241                 win->bpp = 16;
 242                 break;
 243
 244         default:
 245                 debug("Unsupported LCD bit depth");
 246                 return -1;
 247         }
 248
 249         return 0;
 250 }
 251
 252 /**
 253  * Register a new display based on device tree configuration.
 254  *
 255  * The frame buffer can be positioned by U-Boot or overridden by the fdt.
 256  * You should pass in the U-Boot address here, and check the contents of
 257  * struct tegra_lcd_priv to see what was actually chosen.
 258  *
 259  * @param blob                  Device tree blob
 260  * @param priv                  Driver's private data
 261  * @param default_lcd_base      Default address of LCD frame buffer
 262  * @return 0 if ok, -1 on error (unsupported bits per pixel)
 263  */
 264 static int tegra_display_probe(const void *blob, struct tegra_lcd_priv *priv,
 265                                void *default_lcd_base)
 266 {
 267         struct disp_ctl_win window;
 268         struct dc_ctlr *dc;
 269
 270         priv->frame_buffer = (u32)default_lcd_base;
 271
 272         dc = (struct dc_ctlr *)priv->disp;
 273
 274         /*
 275          * A header file for clock constants was NAKed upstream.
 276          * TODO: Put this into the FDT and fdt_lcd struct when we have clock
 277          * support there
 278          */
 279         clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
 280                                144 * 1000000);
 281         clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
 282                                600 * 1000000);
 283         basic_init(&dc->cmd);
 284         basic_init_timer(&dc->disp);
 285         rgb_enable(&dc->com);
 286
 287         if (priv->pixel_clock)
 288                 update_display_mode(&dc->disp, priv);
 289
 290         if (setup_window(&window, priv))
 291                 return -1;
 292
 293         update_window(dc, &window);
 294
 295         return 0;
 296 }
 297
 298 static int tegra_lcd_probe(struct udevice *dev)
 299 {
 300         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 301         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 302         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 303         const void *blob = gd->fdt_blob;
 304         int ret;
 305
 306         /* Initialize the Tegra display controller */
 307         funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
 308         if (tegra_display_probe(blob, priv, (void *)plat->base)) {
 309                 printf("%s: Failed to probe display driver\n", __func__);
 310                 return -1;
 311         }
 312
 313         pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
 314         pinmux_tristate_disable(PMUX_PINGRP_GPU);
 315
 316         ret = panel_enable_backlight(priv->panel);
 317         if (ret) {
 318                 debug("%s: Cannot enable backlight, ret=%d\n", __func__, ret);
 319                 return ret;
 320         }
 321
 322         mmu_set_region_dcache_behaviour(priv->frame_buffer, plat->size,
 323                                         DCACHE_WRITETHROUGH);
 324
 325         /* Enable flushing after LCD writes if requested */
 326         video_set_flush_dcache(dev, true);
 327
 328         uc_priv->xsize = priv->width;
 329         uc_priv->ysize = priv->height;
 330         uc_priv->bpix = priv->log2_bpp;
 331         debug("LCD frame buffer at %pa, size %x\n", &priv->frame_buffer,
 332               plat->size);
 333
 334         return 0;
 335 }
 336
 337 static int tegra_lcd_ofdata_to_platdata(struct udevice *dev)
 338 {
 339         struct tegra_lcd_priv *priv = dev_get_priv(dev);
 340         const void *blob = gd->fdt_blob;
 341         struct display_timing *timing;
 342         int node = dev_of_offset(dev);
 343         int panel_node;
 344         int rgb;
 345         int ret;
 346
 347         priv->disp = (struct disp_ctlr *)devfdt_get_addr(dev);
 348         if (!priv->disp) {
 349                 debug("%s: No display controller address\n", __func__);
 350                 return -EINVAL;
 351         }
 352
 353         rgb = fdt_subnode_offset(blob, node, "rgb");
 354         if (rgb < 0) {
 355                 debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n",
 356                       __func__, dev->name, rgb);
 357                 return -EINVAL;
 358         }
 359
 360         ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing);
 361         if (ret) {
 362                 debug("%s: Cannot read display timing for '%s' (ret=%d)\n",
 363                       __func__, dev->name, ret);
 364                 return -EINVAL;
 365         }
 366         timing = &priv->timing;
 367         priv->width = timing->hactive.typ;
 368         priv->height = timing->vactive.typ;
 369         priv->pixel_clock = timing->pixelclock.typ;
 370         priv->log2_bpp = VIDEO_BPP16;
 371
 372         /*
 373          * Sadly the panel phandle is in an rgb subnode so we cannot use
 374          * uclass_get_device_by_phandle().
 375          */
 376         panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
 377         if (panel_node < 0) {
 378                 debug("%s: Cannot find panel information\n", __func__);
 379                 return -EINVAL;
 380         }
 381         ret = uclass_get_device_by_of_offset(UCLASS_PANEL, panel_node,
 382                                              &priv->panel);
 383         if (ret) {
 384                 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
 385                       dev->name, ret);
 386                 return ret;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int tegra_lcd_bind(struct udevice *dev)
 393 {
 394         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 395         const void *blob = gd->fdt_blob;
 396         int node = dev_of_offset(dev);
 397         int rgb;
 398
 399         rgb = fdt_subnode_offset(blob, node, "rgb");
 400         if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb))
 401                 return -ENODEV;
 402
 403         plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
 404                 (1 << LCD_MAX_LOG2_BPP) / 8;
 405
 406         return 0;
 407 }
 408
 409 static const struct video_ops tegra_lcd_ops = {
 410 };
 411
 412 static const struct udevice_id tegra_lcd_ids[] = {
 413         { .compatible = "nvidia,tegra20-dc" },
 414         { }
 415 };
 416
 417 U_BOOT_DRIVER(tegra_lcd) = {
 418         .name   = "tegra_lcd",
 419         .id     = UCLASS_VIDEO,
 420         .of_match = tegra_lcd_ids,
 421         .ops    = &tegra_lcd_ops,
 422         .bind   = tegra_lcd_bind,
 423         .probe  = tegra_lcd_probe,
 424         .ofdata_to_platdata     = tegra_lcd_ofdata_to_platdata,
 425         .priv_auto_alloc_size   = sizeof(struct tegra_lcd_priv),
 426 };