drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <fdtdec.h>
  18 #include <fdt_support.h>
  19 #include <video_fb.h>
  20 #include "videomodes.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct sunxi_display {
  25         GraphicDevice graphic_device;
  26         bool enabled;
  27 } sunxi_display;
  28
  29 /*
  30  * Wait up to 200ms for value to be set in given part of reg.
  31  */
  32 static int await_completion(u32 *reg, u32 mask, u32 val)
  33 {
  34         unsigned long tmo = timer_get_us() + 200000;
  35
  36         while ((readl(reg) & mask) != val) {
  37                 if (timer_get_us() > tmo) {
  38                         printf("DDC: timeout reading EDID\n");
  39                         return -ETIME;
  40                 }
  41         }
  42         return 0;
  43 }
  44
  45 static int sunxi_hdmi_hpd_detect(void)
  46 {
  47         struct sunxi_ccm_reg * const ccm =
  48                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  49         struct sunxi_hdmi_reg * const hdmi =
  50                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  51
  52         /* Set pll3 to 300MHz */
  53         clock_set_pll3(300000000);
  54
  55         /* Set hdmi parent to pll3 */
  56         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  57                         CCM_HDMI_CTRL_PLL3);
  58
  59         /* Set ahb gating to pass */
  60 #ifdef CONFIG_MACH_SUN6I
  61         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  62 #endif
  63         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  64
  65         /* Clock on */
  66         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  67
  68         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  69         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  70
  71         udelay(1000);
  72
  73         return (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT) ? 1 : 0;
  74 }
  75
  76 static void sunxi_hdmi_shutdown(void)
  77 {
  78         struct sunxi_ccm_reg * const ccm =
  79                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  80         struct sunxi_hdmi_reg * const hdmi =
  81                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  82
  83         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  84         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  85         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  86 #ifdef CONFIG_MACH_SUN6I
  87         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  88 #endif
  89         clock_set_pll3(0);
  90 }
  91
  92 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  93 {
  94         struct sunxi_hdmi_reg * const hdmi =
  95                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  96
  97         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
  98         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
  99                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 100                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 101                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 102 #ifndef CONFIG_MACH_SUN6I
 103         writel(n, &hdmi->ddc_byte_count);
 104         writel(cmnd, &hdmi->ddc_cmnd);
 105 #else
 106         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 107 #endif
 108         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 109
 110         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 111 }
 112
 113 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 114 {
 115         struct sunxi_hdmi_reg * const hdmi =
 116                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 117         int i, n;
 118
 119         while (count > 0) {
 120                 if (count > 16)
 121                         n = 16;
 122                 else
 123                         n = count;
 124
 125                 if (sunxi_hdmi_ddc_do_command(
 126                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 127                                 offset, n))
 128                         return -ETIME;
 129
 130                 for (i = 0; i < n; i++)
 131                         *buf++ = readb(&hdmi->ddc_fifo_data);
 132
 133                 offset += n;
 134                 count -= n;
 135         }
 136
 137         return 0;
 138 }
 139
 140 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 141 {
 142         int r, retries = 2;
 143
 144         do {
 145                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 146                 if (r)
 147                         continue;
 148                 r = edid_check_checksum(buf);
 149                 if (r) {
 150                         printf("EDID block %d: checksum error%s\n",
 151                                block, retries ? ", retrying" : "");
 152                 }
 153         } while (r && retries--);
 154
 155         return r;
 156 }
 157
 158 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode, char *monitor)
 159 {
 160         struct edid1_info edid1;
 161         struct edid_cea861_info cea681[4];
 162         struct edid_detailed_timing *t =
 163                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 164         struct sunxi_hdmi_reg * const hdmi =
 165                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 166         struct sunxi_ccm_reg * const ccm =
 167                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 168         int i, r, ext_blocks = 0;
 169
 170         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 171         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 172                &hdmi->pad_ctrl1);
 173         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 174                &hdmi->pll_ctrl);
 175         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 176
 177         /* Reset i2c controller */
 178         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 179         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 180                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 181                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 182                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 183         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 184                 return -EIO;
 185
 186         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 187 #ifndef CONFIG_MACH_SUN6I
 188         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 189                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 190 #endif
 191
 192         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 193         if (r == 0) {
 194                 r = edid_check_info(&edid1);
 195                 if (r) {
 196                         printf("EDID: invalid EDID data\n");
 197                         r = -EINVAL;
 198                 }
 199         }
 200         if (r == 0) {
 201                 ext_blocks = edid1.extension_flag;
 202                 if (ext_blocks > 4)
 203                         ext_blocks = 4;
 204                 for (i = 0; i < ext_blocks; i++) {
 205                         if (sunxi_hdmi_edid_get_block(1 + i,
 206                                                 (u8 *)&cea681[i]) != 0) {
 207                                 ext_blocks = i;
 208                                 break;
 209                         }
 210                 }
 211         }
 212
 213         /* Disable DDC engine, no longer needed */
 214         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 215         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 216
 217         if (r)
 218                 return r;
 219
 220         /* We want version 1.3 or 1.2 with detailed timing info */
 221         if (edid1.version != 1 || (edid1.revision < 3 &&
 222                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 223                 printf("EDID: unsupported version %d.%d\n",
 224                        edid1.version, edid1.revision);
 225                 return -EINVAL;
 226         }
 227
 228         /* Take the first usable detailed timing */
 229         for (i = 0; i < 4; i++, t++) {
 230                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 231                 if (r == 0)
 232                         break;
 233         }
 234         if (i == 4) {
 235                 printf("EDID: no usable detailed timing found\n");
 236                 return -ENOENT;
 237         }
 238
 239         /* Check for basic audio support, if found enable hdmi output */
 240         strcpy(monitor, "dvi");
 241         for (i = 0; i < ext_blocks; i++) {
 242                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 243                     cea681[i].revision < 2)
 244                         continue;
 245
 246                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 247                         strcpy(monitor, "hdmi");
 248         }
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * This is the entity that mixes and matches the different layers and inputs.
 255  * Allwinner calls it the back-end, but i like composer better.
 256  */
 257 static void sunxi_composer_init(void)
 258 {
 259         struct sunxi_ccm_reg * const ccm =
 260                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 261         struct sunxi_de_be_reg * const de_be =
 262                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 263         int i;
 264
 265 #ifdef CONFIG_MACH_SUN6I
 266         /* Reset off */
 267         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 268 #endif
 269
 270         /* Clocks on */
 271         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 272         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 273         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 274
 275         /* Engine bug, clear registers after reset */
 276         for (i = 0x0800; i < 0x1000; i += 4)
 277                 writel(0, SUNXI_DE_BE0_BASE + i);
 278
 279         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 280 }
 281
 282 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 283                                     unsigned int address)
 284 {
 285         struct sunxi_de_be_reg * const de_be =
 286                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 287
 288         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 289                &de_be->disp_size);
 290         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 291                &de_be->layer0_size);
 292         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 293         writel(address << 3, &de_be->layer0_addr_low32b);
 294         writel(address >> 29, &de_be->layer0_addr_high4b);
 295         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 296
 297         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 298 }
 299
 300 /*
 301  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 302  */
 303 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 304 {
 305         struct sunxi_ccm_reg * const ccm =
 306                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 307         int value, n, m, diff;
 308         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 309         int best_double = 0;
 310
 311         /*
 312          * Find the lowest divider resulting in a matching clock, if there
 313          * is no match, pick the closest lower clock, as monitors tend to
 314          * not sync to higher frequencies.
 315          */
 316         for (m = 15; m > 0; m--) {
 317                 n = (m * dotclock) / 3000;
 318
 319                 if ((n >= 9) && (n <= 127)) {
 320                         value = (3000 * n) / m;
 321                         diff = dotclock - value;
 322                         if (diff < best_diff) {
 323                                 best_diff = diff;
 324                                 best_m = m;
 325                                 best_n = n;
 326                                 best_double = 0;
 327                         }
 328                 }
 329
 330                 /* These are just duplicates */
 331                 if (!(m & 1))
 332                         continue;
 333
 334                 n = (m * dotclock) / 6000;
 335                 if ((n >= 9) && (n <= 127)) {
 336                         value = (6000 * n) / m;
 337                         diff = dotclock - value;
 338                         if (diff < best_diff) {
 339                                 best_diff = diff;
 340                                 best_m = m;
 341                                 best_n = n;
 342                                 best_double = 1;
 343                         }
 344                 }
 345         }
 346
 347         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 348               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 349               best_double + 1, best_n, best_m);
 350
 351         clock_set_pll3(best_n * 3000000);
 352
 353         writel(CCM_LCD_CH1_CTRL_GATE |
 354             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 355             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 356
 357         *clk_div = best_m;
 358         *clk_double = best_double;
 359 }
 360
 361 static void sunxi_lcdc_init(void)
 362 {
 363         struct sunxi_ccm_reg * const ccm =
 364                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 365         struct sunxi_lcdc_reg * const lcdc =
 366                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 367
 368         /* Reset off */
 369 #ifdef CONFIG_MACH_SUN6I
 370         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 371 #else
 372         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 373 #endif
 374
 375         /* Clock on */
 376         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 377
 378         /* Init lcdc */
 379         writel(0, &lcdc->ctrl); /* Disable tcon */
 380         writel(0, &lcdc->int0); /* Disable all interrupts */
 381
 382         /* Disable tcon0 dot clock */
 383         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 384
 385         /* Set all io lines to tristate */
 386         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 387         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 388 }
 389
 390 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 391                                 int *clk_div, int *clk_double)
 392 {
 393         struct sunxi_lcdc_reg * const lcdc =
 394                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 395         int bp, total;
 396
 397         /* Use tcon1 */
 398         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 399                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 400
 401         /* Enabled, 0x1e start delay */
 402         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 403                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 404
 405         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 406                &lcdc->tcon1_timing_source);
 407         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 408                &lcdc->tcon1_timing_scale);
 409         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 410                &lcdc->tcon1_timing_out);
 411
 412         bp = mode->hsync_len + mode->left_margin;
 413         total = mode->xres + mode->right_margin + bp;
 414         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 415                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 416
 417         bp = mode->vsync_len + mode->upper_margin;
 418         total = mode->yres + mode->lower_margin + bp;
 419         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 420                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 421
 422         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 423                &lcdc->tcon1_timing_sync);
 424
 425         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 426 }
 427
 428 #ifdef CONFIG_MACH_SUN6I
 429 static void sunxi_drc_init(void)
 430 {
 431         struct sunxi_ccm_reg * const ccm =
 432                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 433
 434         /* On sun6i the drc must be clocked even when in pass-through mode */
 435         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 436         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 437 }
 438 #endif
 439
 440 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 441 {
 442         struct sunxi_hdmi_reg * const hdmi =
 443                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 444         u8 checksum = 0;
 445         u8 avi_info_frame[17] = {
 446                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 447                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 448                 0x00
 449         };
 450         u8 vendor_info_frame[19] = {
 451                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 452                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 453                 0x00, 0x00, 0x00
 454         };
 455         int i;
 456
 457         if (mode->pixclock_khz <= 27000)
 458                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 459         else
 460                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 461
 462         if (mode->xres * 100 / mode->yres < 156)
 463                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 464         else
 465                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 466
 467         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 468                 checksum += avi_info_frame[i];
 469
 470         avi_info_frame[3] = 0x100 - checksum;
 471
 472         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 473                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 474
 475         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 476         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 477
 478         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 479                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 480
 481         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 482         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 483
 484         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 485 }
 486
 487 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 488                                 bool hdmi_mode, int clk_div, int clk_double)
 489 {
 490         struct sunxi_hdmi_reg * const hdmi =
 491                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 492         int x, y;
 493
 494         /* Write clear interrupt status bits */
 495         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 496
 497         if (hdmi_mode)
 498                 sunxi_hdmi_setup_info_frames(mode);
 499
 500         /* Init various registers, select pll3 as clock source */
 501         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 502         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 503         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 504         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 505         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 506
 507         /* Setup clk div and doubler */
 508         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 509                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 510         if (!clk_double)
 511                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 512
 513         /* Setup timing registers */
 514         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 515                &hdmi->video_size);
 516
 517         x = mode->hsync_len + mode->left_margin;
 518         y = mode->vsync_len + mode->upper_margin;
 519         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 520
 521         x = mode->right_margin;
 522         y = mode->lower_margin;
 523         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 524
 525         x = mode->hsync_len;
 526         y = mode->vsync_len;
 527         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 528
 529         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 530                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 531
 532         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 533                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 534 }
 535
 536 static void sunxi_engines_init(void)
 537 {
 538         sunxi_composer_init();
 539         sunxi_lcdc_init();
 540 #ifdef CONFIG_MACH_SUN6I
 541         sunxi_drc_init();
 542 #endif
 543 }
 544
 545 static void sunxi_mode_set(const struct ctfb_res_modes *mode, char *monitor,
 546                            unsigned int address)
 547 {
 548         struct sunxi_de_be_reg * const de_be =
 549                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 550         struct sunxi_lcdc_reg * const lcdc =
 551                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 552         struct sunxi_hdmi_reg * const hdmi =
 553                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 554         int clk_div, clk_double;
 555         int retries = 3;
 556         bool hdmi_mode = strcmp(monitor, "hdmi") == 0;
 557
 558 retry:
 559         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 560         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 561         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 562
 563         sunxi_composer_mode_set(mode, address);
 564         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 565         sunxi_hdmi_mode_set(mode, hdmi_mode, clk_div, clk_double);
 566
 567         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 568         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 569
 570         udelay(1000000 / mode->refresh + 500);
 571
 572         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 573
 574         udelay(1000000 / mode->refresh + 500);
 575
 576         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 577
 578         udelay(1000000 / mode->refresh + 500);
 579
 580         /*
 581          * Sometimes the display pipeline does not sync up properly, if
 582          * this happens the hdmi fifo underrun or overrun bits are set.
 583          */
 584         if (readl(&hdmi->irq) &
 585             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 586                 if (retries--)
 587                         goto retry;
 588                 printf("HDMI fifo under or overrun\n");
 589         }
 590 }
 591
 592 void *video_hw_init(void)
 593 {
 594         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 595         const struct ctfb_res_modes *mode;
 596         struct ctfb_res_modes edid_mode;
 597         const char *options;
 598         unsigned int depth;
 599         int ret, hpd, edid;
 600         char monitor[16];
 601
 602         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 603
 604         printf("Reserved %dkB of RAM for Framebuffer.\n",
 605                CONFIG_SUNXI_FB_SIZE >> 10);
 606         gd->fb_base = gd->ram_top;
 607
 608         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 609         hpd = video_get_option_int(options, "hpd", 1);
 610         edid = video_get_option_int(options, "edid", 1);
 611         video_get_option_string(options, "monitor", monitor, sizeof(monitor),
 612                                 "dvi");
 613
 614         /* Always call hdp_detect, as it also enables various clocks, etc. */
 615         ret = sunxi_hdmi_hpd_detect();
 616         if (hpd && !ret) {
 617                 sunxi_hdmi_shutdown();
 618                 return NULL;
 619         }
 620         if (ret)
 621                 printf("HDMI connected: ");
 622
 623         /* Check edid if requested and we've a cable plugged in */
 624         if (edid && ret) {
 625                 if (sunxi_hdmi_edid_get_mode(&edid_mode, monitor) == 0)
 626                         mode = &edid_mode;
 627         }
 628
 629         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 630                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 631                 mode = &res_mode_init[RES_MODE_1024x768];
 632         } else {
 633                 printf("Setting up a %dx%d %s console\n",
 634                        mode->xres, mode->yres, monitor);
 635         }
 636
 637         sunxi_display.enabled = true;
 638         sunxi_engines_init();
 639         sunxi_mode_set(mode, monitor, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 640
 641         /*
 642          * These are the only members of this structure that are used. All the
 643          * others are driver specific. There is nothing to decribe pitch or
 644          * stride, but we are lucky with our hw.
 645          */
 646         graphic_device->frameAdrs = gd->fb_base;
 647         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 648         graphic_device->gdfBytesPP = 4;
 649         graphic_device->winSizeX = mode->xres;
 650         graphic_device->winSizeY = mode->yres;
 651
 652         return graphic_device;
 653 }
 654
 655 /*
 656  * Simplefb support.
 657  */
 658 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 659 int sunxi_simplefb_setup(void *blob)
 660 {
 661         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 662         int offset, ret;
 663
 664         if (!sunxi_display.enabled)
 665                 return 0;
 666
 667         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 668         offset = fdt_node_offset_by_compatible(blob, -1,
 669                                                "allwinner,simple-framebuffer");
 670         while (offset >= 0) {
 671                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 672                                       "de_be0-lcd0-hdmi");
 673                 if (ret == 0)
 674                         break;
 675                 offset = fdt_node_offset_by_compatible(blob, offset,
 676                                                "allwinner,simple-framebuffer");
 677         }
 678         if (offset < 0) {
 679                 eprintf("Cannot setup simplefb: node not found\n");
 680                 return 0; /* Keep older kernels working */
 681         }
 682
 683         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 684                         graphic_device->winSizeX, graphic_device->winSizeY,
 685                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 686                         "x8r8g8b8");
 687         if (ret)
 688                 eprintf("Cannot setup simplefb: Error setting properties\n");
 689
 690         return ret;
 691 }
 692 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */