2 * Display driver for Allwinner SoCs.
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/display.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/global_data.h>
20 #include <fdt_support.h>
22 #include "videomodes.h"
25 DECLARE_GLOBAL_DATA_PTR;
34 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
36 struct sunxi_display {
37 GraphicDevice graphic_device;
38 enum sunxi_monitor monitor;
42 #ifdef CONFIG_VIDEO_HDMI
45 * Wait up to 200ms for value to be set in given part of reg.
47 static int await_completion(u32 *reg, u32 mask, u32 val)
49 unsigned long tmo = timer_get_us() + 200000;
51 while ((readl(reg) & mask) != val) {
52 if (timer_get_us() > tmo) {
53 printf("DDC: timeout reading EDID\n");
60 static int sunxi_hdmi_hpd_detect(int hpd_delay)
62 struct sunxi_ccm_reg * const ccm =
63 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
64 struct sunxi_hdmi_reg * const hdmi =
65 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
66 unsigned long tmo = timer_get_us() + hpd_delay * 1000;
68 /* Set pll3 to 300MHz */
69 clock_set_pll3(300000000);
71 /* Set hdmi parent to pll3 */
72 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
75 /* Set ahb gating to pass */
76 #ifdef CONFIG_MACH_SUN6I
77 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
79 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
82 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
84 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
85 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
87 while (timer_get_us() < tmo) {
88 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
95 static void sunxi_hdmi_shutdown(void)
97 struct sunxi_ccm_reg * const ccm =
98 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
99 struct sunxi_hdmi_reg * const hdmi =
100 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
102 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
103 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
104 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
105 #ifdef CONFIG_MACH_SUN6I
106 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
111 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
113 struct sunxi_hdmi_reg * const hdmi =
114 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
116 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
117 writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
118 SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
119 SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
120 SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
121 #ifndef CONFIG_MACH_SUN6I
122 writel(n, &hdmi->ddc_byte_count);
123 writel(cmnd, &hdmi->ddc_cmnd);
125 writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
127 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
129 return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
132 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
134 struct sunxi_hdmi_reg * const hdmi =
135 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
144 if (sunxi_hdmi_ddc_do_command(
145 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
149 for (i = 0; i < n; i++)
150 *buf++ = readb(&hdmi->ddc_fifo_data);
159 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
164 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
167 r = edid_check_checksum(buf);
169 printf("EDID block %d: checksum error%s\n",
170 block, retries ? ", retrying" : "");
172 } while (r && retries--);
177 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
179 struct edid1_info edid1;
180 struct edid_cea861_info cea681[4];
181 struct edid_detailed_timing *t =
182 (struct edid_detailed_timing *)edid1.monitor_details.timing;
183 struct sunxi_hdmi_reg * const hdmi =
184 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
185 struct sunxi_ccm_reg * const ccm =
186 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
187 int i, r, ext_blocks = 0;
189 /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
190 writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
192 writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
194 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
196 /* Reset i2c controller */
197 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
198 writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
199 SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
200 SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
201 SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
202 if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
205 writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
206 #ifndef CONFIG_MACH_SUN6I
207 writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
208 SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
211 r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
213 r = edid_check_info(&edid1);
215 printf("EDID: invalid EDID data\n");
220 ext_blocks = edid1.extension_flag;
223 for (i = 0; i < ext_blocks; i++) {
224 if (sunxi_hdmi_edid_get_block(1 + i,
225 (u8 *)&cea681[i]) != 0) {
232 /* Disable DDC engine, no longer needed */
233 clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
234 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
239 /* We want version 1.3 or 1.2 with detailed timing info */
240 if (edid1.version != 1 || (edid1.revision < 3 &&
241 !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
242 printf("EDID: unsupported version %d.%d\n",
243 edid1.version, edid1.revision);
247 /* Take the first usable detailed timing */
248 for (i = 0; i < 4; i++, t++) {
249 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
254 printf("EDID: no usable detailed timing found\n");
258 /* Check for basic audio support, if found enable hdmi output */
259 sunxi_display.monitor = sunxi_monitor_dvi;
260 for (i = 0; i < ext_blocks; i++) {
261 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
262 cea681[i].revision < 2)
265 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
266 sunxi_display.monitor = sunxi_monitor_hdmi;
272 #endif /* CONFIG_VIDEO_HDMI */
275 * This is the entity that mixes and matches the different layers and inputs.
276 * Allwinner calls it the back-end, but i like composer better.
278 static void sunxi_composer_init(void)
280 struct sunxi_ccm_reg * const ccm =
281 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
282 struct sunxi_de_be_reg * const de_be =
283 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
286 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
288 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
292 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
293 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
294 clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
296 /* Engine bug, clear registers after reset */
297 for (i = 0x0800; i < 0x1000; i += 4)
298 writel(0, SUNXI_DE_BE0_BASE + i);
300 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
303 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
304 unsigned int address)
306 struct sunxi_de_be_reg * const de_be =
307 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
309 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
311 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
312 &de_be->layer0_size);
313 writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
314 writel(address << 3, &de_be->layer0_addr_low32b);
315 writel(address >> 29, &de_be->layer0_addr_high4b);
316 writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
318 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
321 static void sunxi_composer_enable(void)
323 struct sunxi_de_be_reg * const de_be =
324 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
326 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
327 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
331 * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
333 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
334 int *clk_div, int *clk_double)
336 struct sunxi_ccm_reg * const ccm =
337 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
338 int value, n, m, min_m, max_m, diff;
339 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
343 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
347 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
356 * Find the lowest divider resulting in a matching clock, if there
357 * is no match, pick the closest lower clock, as monitors tend to
358 * not sync to higher frequencies.
360 for (m = min_m; m <= max_m; m++) {
361 n = (m * dotclock) / 3000;
363 if ((n >= 9) && (n <= 127)) {
364 value = (3000 * n) / m;
365 diff = dotclock - value;
366 if (diff < best_diff) {
374 /* These are just duplicates */
378 n = (m * dotclock) / 6000;
379 if ((n >= 9) && (n <= 127)) {
380 value = (6000 * n) / m;
381 diff = dotclock - value;
382 if (diff < best_diff) {
391 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
392 dotclock, (best_double + 1) * 3000 * best_n / best_m,
393 best_double + 1, best_n, best_m);
395 clock_set_pll3(best_n * 3000000);
398 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
399 (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
400 CCM_LCD_CH0_CTRL_PLL3),
401 &ccm->lcd0_ch0_clk_cfg);
403 writel(CCM_LCD_CH1_CTRL_GATE |
404 (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
405 CCM_LCD_CH1_CTRL_PLL3) |
406 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
410 *clk_double = best_double;
413 static void sunxi_lcdc_init(void)
415 struct sunxi_ccm_reg * const ccm =
416 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
417 struct sunxi_lcdc_reg * const lcdc =
418 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
421 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
422 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
424 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
428 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
429 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
430 setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
434 writel(0, &lcdc->ctrl); /* Disable tcon */
435 writel(0, &lcdc->int0); /* Disable all interrupts */
437 /* Disable tcon0 dot clock */
438 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
440 /* Set all io lines to tristate */
441 writel(0xffffffff, &lcdc->tcon0_io_tristate);
442 writel(0xffffffff, &lcdc->tcon1_io_tristate);
445 static void sunxi_lcdc_enable(void)
447 struct sunxi_lcdc_reg * const lcdc =
448 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
450 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
451 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
452 setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
453 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
454 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
455 udelay(2); /* delay at least 1200 ns */
456 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
457 udelay(1); /* delay at least 120 ns */
458 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
459 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
463 static void sunxi_lcdc_panel_enable(void)
468 * Start with backlight disabled to avoid the screen flashing to
469 * white while the lcd inits.
471 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
473 gpio_request(pin, "lcd_backlight_enable");
474 gpio_direction_output(pin, 0);
477 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
479 gpio_request(pin, "lcd_backlight_pwm");
480 /* backlight pwm is inverted, set to 1 to disable backlight */
481 gpio_direction_output(pin, 1);
484 /* Give the backlight some time to turn off and power up the panel. */
486 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
488 gpio_request(pin, "lcd_power");
489 gpio_direction_output(pin, 1);
493 static void sunxi_lcdc_backlight_enable(void)
498 * We want to have scanned out at least one frame before enabling the
499 * backlight to avoid the screen flashing to white when we enable it.
503 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
505 gpio_direction_output(pin, 1);
507 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
509 /* backlight pwm is inverted, set to 0 to enable backlight */
510 gpio_direction_output(pin, 0);
514 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
518 delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
519 return (delay > 30) ? 30 : delay;
522 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
524 struct sunxi_lcdc_reg * const lcdc =
525 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
526 int bp, clk_delay, clk_div, clk_double, pin, total, val;
528 for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
529 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
530 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
532 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
533 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
536 sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
539 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
540 SUNXI_LCDC_CTRL_IO_MAP_TCON0);
542 clk_delay = sunxi_lcdc_get_clk_delay(mode);
543 writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
544 SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
546 writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
547 SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
549 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
550 &lcdc->tcon0_timing_active);
552 bp = mode->hsync_len + mode->left_margin;
553 total = mode->xres + mode->right_margin + bp;
554 writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
555 SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
557 bp = mode->vsync_len + mode->upper_margin;
558 total = mode->yres + mode->lower_margin + bp;
559 writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
560 SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
562 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
563 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
564 &lcdc->tcon0_timing_sync);
566 writel(0, &lcdc->tcon0_hv_intf);
567 writel(0, &lcdc->tcon0_cpu_intf);
569 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
570 val = (sunxi_display.depth == 18) ? 1 : 0;
571 writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf);
574 if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
575 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
576 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
577 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
578 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
579 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
580 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
581 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
582 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
583 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
584 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
585 writel(((sunxi_display.depth == 18) ?
586 SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
587 SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
588 &lcdc->tcon0_frm_ctrl);
591 val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
592 if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
593 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
594 if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
595 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
596 writel(val, &lcdc->tcon0_io_polarity);
598 writel(0, &lcdc->tcon0_io_tristate);
601 #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA
602 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
603 int *clk_div, int *clk_double,
604 bool use_portd_hvsync)
606 struct sunxi_lcdc_reg * const lcdc =
607 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
608 int bp, clk_delay, total, val;
611 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
612 SUNXI_LCDC_CTRL_IO_MAP_TCON1);
614 clk_delay = sunxi_lcdc_get_clk_delay(mode);
615 writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
616 SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
618 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
619 &lcdc->tcon1_timing_source);
620 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
621 &lcdc->tcon1_timing_scale);
622 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
623 &lcdc->tcon1_timing_out);
625 bp = mode->hsync_len + mode->left_margin;
626 total = mode->xres + mode->right_margin + bp;
627 writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
628 SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
630 bp = mode->vsync_len + mode->upper_margin;
631 total = mode->yres + mode->lower_margin + bp;
632 writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
633 SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
635 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
636 &lcdc->tcon1_timing_sync);
638 if (use_portd_hvsync) {
639 sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
640 sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
643 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
644 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
645 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
646 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
647 writel(val, &lcdc->tcon1_io_polarity);
649 clrbits_le32(&lcdc->tcon1_io_tristate,
650 SUNXI_LCDC_TCON_VSYNC_MASK |
651 SUNXI_LCDC_TCON_HSYNC_MASK);
653 sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
655 #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */
657 #ifdef CONFIG_VIDEO_HDMI
659 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
661 struct sunxi_hdmi_reg * const hdmi =
662 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
664 u8 avi_info_frame[17] = {
665 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
666 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
669 u8 vendor_info_frame[19] = {
670 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
671 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
676 if (mode->pixclock_khz <= 27000)
677 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
679 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
681 if (mode->xres * 100 / mode->yres < 156)
682 avi_info_frame[5] |= 0x18; /* 4 : 3 */
684 avi_info_frame[5] |= 0x28; /* 16 : 9 */
686 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
687 checksum += avi_info_frame[i];
689 avi_info_frame[3] = 0x100 - checksum;
691 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
692 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
694 writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
695 writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
697 for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
698 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
700 writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
701 writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
703 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
706 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
707 int clk_div, int clk_double)
709 struct sunxi_hdmi_reg * const hdmi =
710 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
713 /* Write clear interrupt status bits */
714 writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
716 if (sunxi_display.monitor == sunxi_monitor_hdmi)
717 sunxi_hdmi_setup_info_frames(mode);
719 /* Set input sync enable */
720 writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
722 /* Init various registers, select pll3 as clock source */
723 writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
724 writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
725 writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
726 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
727 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
729 /* Setup clk div and doubler */
730 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
731 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
733 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
735 /* Setup timing registers */
736 writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
739 x = mode->hsync_len + mode->left_margin;
740 y = mode->vsync_len + mode->upper_margin;
741 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
743 x = mode->right_margin;
744 y = mode->lower_margin;
745 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
749 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
751 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
752 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
754 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
755 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
758 static void sunxi_hdmi_enable(void)
760 struct sunxi_hdmi_reg * const hdmi =
761 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
764 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
767 #endif /* CONFIG_VIDEO_HDMI */
769 #ifdef CONFIG_VIDEO_VGA
771 static void sunxi_vga_mode_set(void)
773 struct sunxi_ccm_reg * const ccm =
774 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
775 struct sunxi_tve_reg * const tve =
776 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
779 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
781 /* Set TVE in VGA mode */
782 writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
783 SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
784 SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
785 writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0);
786 writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0);
787 writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1);
790 static void sunxi_vga_enable(void)
792 struct sunxi_tve_reg * const tve =
793 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
795 setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
798 #endif /* CONFIG_VIDEO_VGA */
800 static void sunxi_drc_init(void)
802 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
803 struct sunxi_ccm_reg * const ccm =
804 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
806 /* On sun6i the drc must be clocked even when in pass-through mode */
807 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
808 clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
812 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
813 static void sunxi_vga_external_dac_enable(void)
817 pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
819 gpio_request(pin, "vga_enable");
820 gpio_direction_output(pin, 1);
823 #endif /* CONFIG_VIDEO_VGA_VIA_LCD */
825 #ifdef CONFIG_VIDEO_LCD_SSD2828
826 static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
828 struct ssd2828_config cfg = {
829 .csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
830 .sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
831 .sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
832 .sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
833 .reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
834 .ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
835 .ssd2828_color_depth = 24,
836 #ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
837 .mipi_dsi_number_of_data_lanes = 4,
838 .mipi_dsi_bitrate_per_data_lane_mbps = 513,
839 .mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
840 .mipi_dsi_delay_after_set_display_on_ms = 200
842 #error MIPI LCD panel needs configuration parameters
846 if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
847 printf("SSD2828: SPI pins are not properly configured\n");
850 if (cfg.reset_pin == -1) {
851 printf("SSD2828: Reset pin is not properly configured\n");
855 return ssd2828_init(&cfg, mode);
857 #endif /* CONFIG_VIDEO_LCD_SSD2828 */
859 static void sunxi_engines_init(void)
861 sunxi_composer_init();
866 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
867 unsigned int address)
869 int __maybe_unused clk_div, clk_double;
871 switch (sunxi_display.monitor) {
872 case sunxi_monitor_none:
874 case sunxi_monitor_dvi:
875 case sunxi_monitor_hdmi:
876 #ifdef CONFIG_VIDEO_HDMI
877 sunxi_composer_mode_set(mode, address);
878 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
879 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
880 sunxi_composer_enable();
885 case sunxi_monitor_lcd:
886 sunxi_lcdc_panel_enable();
887 sunxi_composer_mode_set(mode, address);
888 sunxi_lcdc_tcon0_mode_set(mode);
889 sunxi_composer_enable();
891 #ifdef CONFIG_VIDEO_LCD_SSD2828
892 sunxi_ssd2828_init(mode);
894 sunxi_lcdc_backlight_enable();
896 case sunxi_monitor_vga:
897 #ifdef CONFIG_VIDEO_VGA
898 sunxi_composer_mode_set(mode, address);
899 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
900 sunxi_vga_mode_set();
901 sunxi_composer_enable();
904 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
905 sunxi_composer_mode_set(mode, address);
906 sunxi_lcdc_tcon0_mode_set(mode);
907 sunxi_composer_enable();
909 sunxi_vga_external_dac_enable();
915 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
918 case sunxi_monitor_none: return "none";
919 case sunxi_monitor_dvi: return "dvi";
920 case sunxi_monitor_hdmi: return "hdmi";
921 case sunxi_monitor_lcd: return "lcd";
922 case sunxi_monitor_vga: return "vga";
924 return NULL; /* never reached */
927 void *video_hw_init(void)
929 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
930 const struct ctfb_res_modes *mode;
931 struct ctfb_res_modes custom;
933 #ifdef CONFIG_VIDEO_HDMI
934 int ret, hpd, hpd_delay, edid;
937 char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
940 memset(&sunxi_display, 0, sizeof(struct sunxi_display));
942 printf("Reserved %dkB of RAM for Framebuffer.\n",
943 CONFIG_SUNXI_FB_SIZE >> 10);
944 gd->fb_base = gd->ram_top;
946 video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
947 &sunxi_display.depth, &options);
948 #ifdef CONFIG_VIDEO_HDMI
949 hpd = video_get_option_int(options, "hpd", 1);
950 hpd_delay = video_get_option_int(options, "hpd_delay", 500);
951 edid = video_get_option_int(options, "edid", 1);
952 sunxi_display.monitor = sunxi_monitor_dvi;
953 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
954 sunxi_display.monitor = sunxi_monitor_vga;
956 sunxi_display.monitor = sunxi_monitor_lcd;
958 video_get_option_string(options, "monitor", mon, sizeof(mon),
959 sunxi_get_mon_desc(sunxi_display.monitor));
960 for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
961 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
962 sunxi_display.monitor = i;
966 if (i > SUNXI_MONITOR_LAST)
967 printf("Unknown monitor: '%s', falling back to '%s'\n",
968 mon, sunxi_get_mon_desc(sunxi_display.monitor));
970 #ifdef CONFIG_VIDEO_HDMI
971 /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
972 if (sunxi_display.monitor == sunxi_monitor_dvi ||
973 sunxi_display.monitor == sunxi_monitor_hdmi) {
974 /* Always call hdp_detect, as it also enables clocks, etc. */
975 ret = sunxi_hdmi_hpd_detect(hpd_delay);
977 printf("HDMI connected: ");
978 if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
981 sunxi_hdmi_shutdown();
982 /* Fallback to lcd / vga / none */
984 sunxi_display.monitor = sunxi_monitor_lcd;
986 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
987 sunxi_display.monitor = sunxi_monitor_vga;
989 sunxi_display.monitor = sunxi_monitor_none;
992 } /* else continue with hdmi/dvi without a cable connected */
996 switch (sunxi_display.monitor) {
997 case sunxi_monitor_none:
999 case sunxi_monitor_dvi:
1000 case sunxi_monitor_hdmi:
1001 #ifdef CONFIG_VIDEO_HDMI
1004 printf("HDMI/DVI not supported on this board\n");
1005 sunxi_display.monitor = sunxi_monitor_none;
1008 case sunxi_monitor_lcd:
1010 sunxi_display.depth = video_get_params(&custom, lcd_mode);
1014 printf("LCD not supported on this board\n");
1015 sunxi_display.monitor = sunxi_monitor_none;
1017 case sunxi_monitor_vga:
1018 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
1019 sunxi_display.depth = 18;
1022 printf("VGA not supported on this board\n");
1023 sunxi_display.monitor = sunxi_monitor_none;
1028 if (mode->vmode != FB_VMODE_NONINTERLACED) {
1029 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
1030 mode = &res_mode_init[RES_MODE_1024x768];
1032 printf("Setting up a %dx%d %s console\n", mode->xres,
1033 mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
1036 sunxi_engines_init();
1037 sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
1040 * These are the only members of this structure that are used. All the
1041 * others are driver specific. There is nothing to decribe pitch or
1042 * stride, but we are lucky with our hw.
1044 graphic_device->frameAdrs = gd->fb_base;
1045 graphic_device->gdfIndex = GDF_32BIT_X888RGB;
1046 graphic_device->gdfBytesPP = 4;
1047 graphic_device->winSizeX = mode->xres;
1048 graphic_device->winSizeY = mode->yres;
1050 return graphic_device;
1056 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
1057 int sunxi_simplefb_setup(void *blob)
1059 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
1061 const char *pipeline = NULL;
1063 switch (sunxi_display.monitor) {
1064 case sunxi_monitor_none:
1066 case sunxi_monitor_dvi:
1067 case sunxi_monitor_hdmi:
1068 pipeline = "de_be0-lcd0-hdmi";
1070 case sunxi_monitor_lcd:
1071 pipeline = "de_be0-lcd0";
1073 case sunxi_monitor_vga:
1074 #ifdef CONFIG_VIDEO_VGA
1075 pipeline = "de_be0-lcd0-tve0";
1076 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
1077 pipeline = "de_be0-lcd0";
1082 /* Find a prefilled simpefb node, matching out pipeline config */
1083 offset = fdt_node_offset_by_compatible(blob, -1,
1084 "allwinner,simple-framebuffer");
1085 while (offset >= 0) {
1086 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
1090 offset = fdt_node_offset_by_compatible(blob, offset,
1091 "allwinner,simple-framebuffer");
1094 eprintf("Cannot setup simplefb: node not found\n");
1095 return 0; /* Keep older kernels working */
1098 ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
1099 graphic_device->winSizeX, graphic_device->winSizeY,
1100 graphic_device->winSizeX * graphic_device->gdfBytesPP,
1103 eprintf("Cannot setup simplefb: Error setting properties\n");
1107 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */