drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <fdtdec.h>
  17 #include <fdt_support.h>
  18 #include <video_fb.h>
  19 #include "videomodes.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 struct sunxi_display {
  24         GraphicDevice graphic_device;
  25         bool enabled;
  26 } sunxi_display;
  27
  28 static int sunxi_hdmi_hpd_detect(void)
  29 {
  30         struct sunxi_ccm_reg * const ccm =
  31                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  32         struct sunxi_hdmi_reg * const hdmi =
  33                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  34
  35         /* Set pll3 to 300MHz */
  36         clock_set_pll3(300000000);
  37
  38         /* Set hdmi parent to pll3 */
  39         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  40                         CCM_HDMI_CTRL_PLL3);
  41
  42         /* Set ahb gating to pass */
  43 #ifdef CONFIG_MACH_SUN6I
  44         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  45 #endif
  46         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  47
  48         /* Clock on */
  49         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  50
  51         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  52         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  53
  54         udelay(1000);
  55
  56         if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  57                 return 1;
  58
  59         /* No need to keep these running */
  60         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  61         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  62         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  63 #ifdef CONFIG_MACH_SUN6I
  64         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  65 #endif
  66         clock_set_pll3(0);
  67
  68         return 0;
  69 }
  70
  71 /*
  72  * This is the entity that mixes and matches the different layers and inputs.
  73  * Allwinner calls it the back-end, but i like composer better.
  74  */
  75 static void sunxi_composer_init(void)
  76 {
  77         struct sunxi_ccm_reg * const ccm =
  78                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  79         struct sunxi_de_be_reg * const de_be =
  80                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
  81         int i;
  82
  83 #ifdef CONFIG_MACH_SUN6I
  84         /* Reset off */
  85         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
  86 #endif
  87
  88         /* Clocks on */
  89         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
  90         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
  91         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
  92
  93         /* Engine bug, clear registers after reset */
  94         for (i = 0x0800; i < 0x1000; i += 4)
  95                 writel(0, SUNXI_DE_BE0_BASE + i);
  96
  97         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
  98 }
  99
 100 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 101                                     unsigned int address)
 102 {
 103         struct sunxi_de_be_reg * const de_be =
 104                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 105
 106         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 107                &de_be->disp_size);
 108         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 109                &de_be->layer0_size);
 110         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 111         writel(address << 3, &de_be->layer0_addr_low32b);
 112         writel(address >> 29, &de_be->layer0_addr_high4b);
 113         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 114
 115         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 116 }
 117
 118 /*
 119  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 120  */
 121 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 122 {
 123         struct sunxi_ccm_reg * const ccm =
 124                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 125         int value, n, m, diff;
 126         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 127         int best_double = 0;
 128
 129         /*
 130          * Find the lowest divider resulting in a matching clock, if there
 131          * is no match, pick the closest lower clock, as monitors tend to
 132          * not sync to higher frequencies.
 133          */
 134         for (m = 15; m > 0; m--) {
 135                 n = (m * dotclock) / 3000;
 136
 137                 if ((n >= 9) && (n <= 127)) {
 138                         value = (3000 * n) / m;
 139                         diff = dotclock - value;
 140                         if (diff < best_diff) {
 141                                 best_diff = diff;
 142                                 best_m = m;
 143                                 best_n = n;
 144                                 best_double = 0;
 145                         }
 146                 }
 147
 148                 /* These are just duplicates */
 149                 if (!(m & 1))
 150                         continue;
 151
 152                 n = (m * dotclock) / 6000;
 153                 if ((n >= 9) && (n <= 127)) {
 154                         value = (6000 * n) / m;
 155                         diff = dotclock - value;
 156                         if (diff < best_diff) {
 157                                 best_diff = diff;
 158                                 best_m = m;
 159                                 best_n = n;
 160                                 best_double = 1;
 161                         }
 162                 }
 163         }
 164
 165         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 166               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 167               best_double + 1, best_n, best_m);
 168
 169         clock_set_pll3(best_n * 3000000);
 170
 171         writel(CCM_LCD_CH1_CTRL_GATE |
 172             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 173             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 174
 175         *clk_div = best_m;
 176         *clk_double = best_double;
 177 }
 178
 179 static void sunxi_lcdc_init(void)
 180 {
 181         struct sunxi_ccm_reg * const ccm =
 182                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 183         struct sunxi_lcdc_reg * const lcdc =
 184                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 185
 186         /* Reset off */
 187 #ifdef CONFIG_MACH_SUN6I
 188         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 189 #else
 190         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 191 #endif
 192
 193         /* Clock on */
 194         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 195
 196         /* Init lcdc */
 197         writel(0, &lcdc->ctrl); /* Disable tcon */
 198         writel(0, &lcdc->int0); /* Disable all interrupts */
 199
 200         /* Disable tcon0 dot clock */
 201         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 202
 203         /* Set all io lines to tristate */
 204         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 205         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 206 }
 207
 208 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 209                                 int *clk_div, int *clk_double)
 210 {
 211         struct sunxi_lcdc_reg * const lcdc =
 212                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 213         int bp, total;
 214
 215         /* Use tcon1 */
 216         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 217                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 218
 219         /* Enabled, 0x1e start delay */
 220         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 221                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 222
 223         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 224                &lcdc->tcon1_timing_source);
 225         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 226                &lcdc->tcon1_timing_scale);
 227         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 228                &lcdc->tcon1_timing_out);
 229
 230         bp = mode->hsync_len + mode->left_margin;
 231         total = mode->xres + mode->right_margin + bp;
 232         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 233                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 234
 235         bp = mode->vsync_len + mode->upper_margin;
 236         total = mode->yres + mode->lower_margin + bp;
 237         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 238                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 239
 240         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 241                &lcdc->tcon1_timing_sync);
 242
 243         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 244 }
 245
 246 #ifdef CONFIG_MACH_SUN6I
 247 static void sunxi_drc_init(void)
 248 {
 249         struct sunxi_ccm_reg * const ccm =
 250                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 251
 252         /* On sun6i the drc must be clocked even when in pass-through mode */
 253         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 254         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 255 }
 256 #endif
 257
 258 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 259                                 int clk_div, int clk_double)
 260 {
 261         struct sunxi_hdmi_reg * const hdmi =
 262                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 263         int x, y;
 264
 265         /* Write clear interrupt status bits */
 266         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 267
 268         /* Init various registers, select pll3 as clock source */
 269         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 270         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 271         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 272         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 273         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 274
 275         /* Setup clk div and doubler */
 276         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 277                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 278         if (!clk_double)
 279                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 280
 281         /* Setup timing registers */
 282         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 283                &hdmi->video_size);
 284
 285         x = mode->hsync_len + mode->left_margin;
 286         y = mode->vsync_len + mode->upper_margin;
 287         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 288
 289         x = mode->right_margin;
 290         y = mode->lower_margin;
 291         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 292
 293         x = mode->hsync_len;
 294         y = mode->vsync_len;
 295         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 296
 297         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 298                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 299
 300         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 301                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 302 }
 303
 304 static void sunxi_engines_init(void)
 305 {
 306         sunxi_composer_init();
 307         sunxi_lcdc_init();
 308 #ifdef CONFIG_MACH_SUN6I
 309         sunxi_drc_init();
 310 #endif
 311 }
 312
 313 static void sunxi_mode_set(const struct ctfb_res_modes *mode, unsigned int address)
 314 {
 315         struct sunxi_de_be_reg * const de_be =
 316                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 317         struct sunxi_lcdc_reg * const lcdc =
 318                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 319         struct sunxi_hdmi_reg * const hdmi =
 320                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 321         int clk_div, clk_double;
 322         int retries = 3;
 323
 324 retry:
 325         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 326         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 327         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 328
 329         sunxi_composer_mode_set(mode, address);
 330         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 331         sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 332
 333         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 334         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 335
 336         udelay(1000000 / mode->refresh + 500);
 337
 338         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 339
 340         udelay(1000000 / mode->refresh + 500);
 341
 342         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 343
 344         udelay(1000000 / mode->refresh + 500);
 345
 346         /*
 347          * Sometimes the display pipeline does not sync up properly, if
 348          * this happens the hdmi fifo underrun or overrun bits are set.
 349          */
 350         if (readl(&hdmi->irq) &
 351             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 352                 if (retries--)
 353                         goto retry;
 354                 printf("HDMI fifo under or overrun\n");
 355         }
 356 }
 357
 358 void *video_hw_init(void)
 359 {
 360         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 361         const struct ctfb_res_modes *mode;
 362         const char *options;
 363         unsigned int depth;
 364         int ret;
 365
 366         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 367
 368         printf("Reserved %dkB of RAM for Framebuffer.\n",
 369                CONFIG_SUNXI_FB_SIZE >> 10);
 370         gd->fb_base = gd->ram_top;
 371
 372         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 373
 374         ret = sunxi_hdmi_hpd_detect();
 375         if (!ret)
 376                 return NULL;
 377
 378         printf("HDMI connected.\n");
 379
 380         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 381                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 382                 mode = &res_mode_init[RES_MODE_1024x768];
 383         } else {
 384                 printf("Setting up a %dx%d console\n", mode->xres, mode->yres);
 385         }
 386
 387         sunxi_display.enabled = true;
 388         sunxi_engines_init();
 389         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 390
 391         /*
 392          * These are the only members of this structure that are used. All the
 393          * others are driver specific. There is nothing to decribe pitch or
 394          * stride, but we are lucky with our hw.
 395          */
 396         graphic_device->frameAdrs = gd->fb_base;
 397         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 398         graphic_device->gdfBytesPP = 4;
 399         graphic_device->winSizeX = mode->xres;
 400         graphic_device->winSizeY = mode->yres;
 401
 402         return graphic_device;
 403 }
 404
 405 /*
 406  * Simplefb support.
 407  */
 408 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 409 int sunxi_simplefb_setup(void *blob)
 410 {
 411         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 412         int offset, ret;
 413
 414         if (!sunxi_display.enabled)
 415                 return 0;
 416
 417         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 418         offset = fdt_node_offset_by_compatible(blob, -1,
 419                                                "allwinner,simple-framebuffer");
 420         while (offset >= 0) {
 421                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 422                                       "de_be0-lcd0-hdmi");
 423                 if (ret == 0)
 424                         break;
 425                 offset = fdt_node_offset_by_compatible(blob, offset,
 426                                                "allwinner,simple-framebuffer");
 427         }
 428         if (offset < 0) {
 429                 eprintf("Cannot setup simplefb: node not found\n");
 430                 return 0; /* Keep older kernels working */
 431         }
 432
 433         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 434                         graphic_device->winSizeX, graphic_device->winSizeY,
 435                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 436                         "x8r8g8b8");
 437         if (ret)
 438                 eprintf("Cannot setup simplefb: Error setting properties\n");
 439
 440         return ret;
 441 }
 442 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */