drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <errno.h>
  19 #include <fdtdec.h>
  20 #include <fdt_support.h>
  21 #include <video_fb.h>
  22 #include "videomodes.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sunxi_monitor {
  27         sunxi_monitor_none,
  28         sunxi_monitor_dvi,
  29         sunxi_monitor_hdmi,
  30         sunxi_monitor_lcd,
  31         sunxi_monitor_vga,
  32 };
  33 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  34
  35 struct sunxi_display {
  36         GraphicDevice graphic_device;
  37         enum sunxi_monitor monitor;
  38         unsigned int depth;
  39 } sunxi_display;
  40
  41 #ifdef CONFIG_VIDEO_HDMI
  42
  43 /*
  44  * Wait up to 200ms for value to be set in given part of reg.
  45  */
  46 static int await_completion(u32 *reg, u32 mask, u32 val)
  47 {
  48         unsigned long tmo = timer_get_us() + 200000;
  49
  50         while ((readl(reg) & mask) != val) {
  51                 if (timer_get_us() > tmo) {
  52                         printf("DDC: timeout reading EDID\n");
  53                         return -ETIME;
  54                 }
  55         }
  56         return 0;
  57 }
  58
  59 static int sunxi_hdmi_hpd_detect(int hpd_delay)
  60 {
  61         struct sunxi_ccm_reg * const ccm =
  62                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  63         struct sunxi_hdmi_reg * const hdmi =
  64                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  65         unsigned long tmo = timer_get_us() + hpd_delay * 1000;
  66
  67         /* Set pll3 to 300MHz */
  68         clock_set_pll3(300000000);
  69
  70         /* Set hdmi parent to pll3 */
  71         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  72                         CCM_HDMI_CTRL_PLL3);
  73
  74         /* Set ahb gating to pass */
  75 #ifdef CONFIG_MACH_SUN6I
  76         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  77 #endif
  78         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  79
  80         /* Clock on */
  81         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  82
  83         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  84         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  85
  86         while (timer_get_us() < tmo) {
  87                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  88                         return 1;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static void sunxi_hdmi_shutdown(void)
  95 {
  96         struct sunxi_ccm_reg * const ccm =
  97                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  98         struct sunxi_hdmi_reg * const hdmi =
  99                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 100
 101         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
 102         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 103         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 104 #ifdef CONFIG_MACH_SUN6I
 105         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 106 #endif
 107         clock_set_pll3(0);
 108 }
 109
 110 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 111 {
 112         struct sunxi_hdmi_reg * const hdmi =
 113                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 114
 115         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 116         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 117                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 118                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 119                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 120 #ifndef CONFIG_MACH_SUN6I
 121         writel(n, &hdmi->ddc_byte_count);
 122         writel(cmnd, &hdmi->ddc_cmnd);
 123 #else
 124         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 125 #endif
 126         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 127
 128         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 129 }
 130
 131 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 132 {
 133         struct sunxi_hdmi_reg * const hdmi =
 134                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 135         int i, n;
 136
 137         while (count > 0) {
 138                 if (count > 16)
 139                         n = 16;
 140                 else
 141                         n = count;
 142
 143                 if (sunxi_hdmi_ddc_do_command(
 144                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 145                                 offset, n))
 146                         return -ETIME;
 147
 148                 for (i = 0; i < n; i++)
 149                         *buf++ = readb(&hdmi->ddc_fifo_data);
 150
 151                 offset += n;
 152                 count -= n;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 159 {
 160         int r, retries = 2;
 161
 162         do {
 163                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 164                 if (r)
 165                         continue;
 166                 r = edid_check_checksum(buf);
 167                 if (r) {
 168                         printf("EDID block %d: checksum error%s\n",
 169                                block, retries ? ", retrying" : "");
 170                 }
 171         } while (r && retries--);
 172
 173         return r;
 174 }
 175
 176 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 177 {
 178         struct edid1_info edid1;
 179         struct edid_cea861_info cea681[4];
 180         struct edid_detailed_timing *t =
 181                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 182         struct sunxi_hdmi_reg * const hdmi =
 183                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 184         struct sunxi_ccm_reg * const ccm =
 185                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 186         int i, r, ext_blocks = 0;
 187
 188         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 189         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 190                &hdmi->pad_ctrl1);
 191         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 192                &hdmi->pll_ctrl);
 193         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 194
 195         /* Reset i2c controller */
 196         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 197         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 198                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 199                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 200                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 201         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 202                 return -EIO;
 203
 204         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 205 #ifndef CONFIG_MACH_SUN6I
 206         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 207                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 208 #endif
 209
 210         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 211         if (r == 0) {
 212                 r = edid_check_info(&edid1);
 213                 if (r) {
 214                         printf("EDID: invalid EDID data\n");
 215                         r = -EINVAL;
 216                 }
 217         }
 218         if (r == 0) {
 219                 ext_blocks = edid1.extension_flag;
 220                 if (ext_blocks > 4)
 221                         ext_blocks = 4;
 222                 for (i = 0; i < ext_blocks; i++) {
 223                         if (sunxi_hdmi_edid_get_block(1 + i,
 224                                                 (u8 *)&cea681[i]) != 0) {
 225                                 ext_blocks = i;
 226                                 break;
 227                         }
 228                 }
 229         }
 230
 231         /* Disable DDC engine, no longer needed */
 232         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 233         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 234
 235         if (r)
 236                 return r;
 237
 238         /* We want version 1.3 or 1.2 with detailed timing info */
 239         if (edid1.version != 1 || (edid1.revision < 3 &&
 240                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 241                 printf("EDID: unsupported version %d.%d\n",
 242                        edid1.version, edid1.revision);
 243                 return -EINVAL;
 244         }
 245
 246         /* Take the first usable detailed timing */
 247         for (i = 0; i < 4; i++, t++) {
 248                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 249                 if (r == 0)
 250                         break;
 251         }
 252         if (i == 4) {
 253                 printf("EDID: no usable detailed timing found\n");
 254                 return -ENOENT;
 255         }
 256
 257         /* Check for basic audio support, if found enable hdmi output */
 258         sunxi_display.monitor = sunxi_monitor_dvi;
 259         for (i = 0; i < ext_blocks; i++) {
 260                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 261                     cea681[i].revision < 2)
 262                         continue;
 263
 264                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 265                         sunxi_display.monitor = sunxi_monitor_hdmi;
 266         }
 267
 268         return 0;
 269 }
 270
 271 #endif /* CONFIG_VIDEO_HDMI */
 272
 273 /*
 274  * This is the entity that mixes and matches the different layers and inputs.
 275  * Allwinner calls it the back-end, but i like composer better.
 276  */
 277 static void sunxi_composer_init(void)
 278 {
 279         struct sunxi_ccm_reg * const ccm =
 280                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 281         struct sunxi_de_be_reg * const de_be =
 282                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 283         int i;
 284
 285 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 286         /* Reset off */
 287         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 288 #endif
 289
 290         /* Clocks on */
 291         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 292         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 293         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 294
 295         /* Engine bug, clear registers after reset */
 296         for (i = 0x0800; i < 0x1000; i += 4)
 297                 writel(0, SUNXI_DE_BE0_BASE + i);
 298
 299         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 300 }
 301
 302 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 303                                     unsigned int address)
 304 {
 305         struct sunxi_de_be_reg * const de_be =
 306                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 307
 308         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 309                &de_be->disp_size);
 310         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 311                &de_be->layer0_size);
 312         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 313         writel(address << 3, &de_be->layer0_addr_low32b);
 314         writel(address >> 29, &de_be->layer0_addr_high4b);
 315         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 316
 317         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 318 }
 319
 320 static void sunxi_composer_enable(void)
 321 {
 322         struct sunxi_de_be_reg * const de_be =
 323                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 324
 325         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 326         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 327 }
 328
 329 /*
 330  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 331  */
 332 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
 333                                int *clk_div, int *clk_double)
 334 {
 335         struct sunxi_ccm_reg * const ccm =
 336                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 337         int value, n, m, min_m, max_m, diff;
 338         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 339         int best_double = 0;
 340
 341         if (tcon == 0) {
 342 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 343                 min_m = 6;
 344                 max_m = 127;
 345 #endif
 346 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 347                 min_m = max_m = 7;
 348 #endif
 349         } else {
 350                 min_m = 1;
 351                 max_m = 15;
 352         }
 353
 354         /*
 355          * Find the lowest divider resulting in a matching clock, if there
 356          * is no match, pick the closest lower clock, as monitors tend to
 357          * not sync to higher frequencies.
 358          */
 359         for (m = min_m; m <= max_m; m++) {
 360                 n = (m * dotclock) / 3000;
 361
 362                 if ((n >= 9) && (n <= 127)) {
 363                         value = (3000 * n) / m;
 364                         diff = dotclock - value;
 365                         if (diff < best_diff) {
 366                                 best_diff = diff;
 367                                 best_m = m;
 368                                 best_n = n;
 369                                 best_double = 0;
 370                         }
 371                 }
 372
 373                 /* These are just duplicates */
 374                 if (!(m & 1))
 375                         continue;
 376
 377                 n = (m * dotclock) / 6000;
 378                 if ((n >= 9) && (n <= 127)) {
 379                         value = (6000 * n) / m;
 380                         diff = dotclock - value;
 381                         if (diff < best_diff) {
 382                                 best_diff = diff;
 383                                 best_m = m;
 384                                 best_n = n;
 385                                 best_double = 1;
 386                         }
 387                 }
 388         }
 389
 390         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 391               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 392               best_double + 1, best_n, best_m);
 393
 394         clock_set_pll3(best_n * 3000000);
 395
 396         if (tcon == 0) {
 397                 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
 398                        (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
 399                                       CCM_LCD_CH0_CTRL_PLL3),
 400                        &ccm->lcd0_ch0_clk_cfg);
 401         } else {
 402                 writel(CCM_LCD_CH1_CTRL_GATE |
 403                        (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
 404                                       CCM_LCD_CH1_CTRL_PLL3) |
 405                        CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 406         }
 407
 408         *clk_div = best_m;
 409         *clk_double = best_double;
 410 }
 411
 412 static void sunxi_lcdc_init(void)
 413 {
 414         struct sunxi_ccm_reg * const ccm =
 415                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 416         struct sunxi_lcdc_reg * const lcdc =
 417                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 418
 419         /* Reset off */
 420 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 421         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 422 #else
 423         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 424 #endif
 425
 426         /* Clock on */
 427         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 428 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 429         setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
 430 #endif
 431
 432         /* Init lcdc */
 433         writel(0, &lcdc->ctrl); /* Disable tcon */
 434         writel(0, &lcdc->int0); /* Disable all interrupts */
 435
 436         /* Disable tcon0 dot clock */
 437         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 438
 439         /* Set all io lines to tristate */
 440         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 441         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 442 }
 443
 444 static void sunxi_lcdc_enable(void)
 445 {
 446         struct sunxi_lcdc_reg * const lcdc =
 447                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 448
 449         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 450 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 451         setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE);
 452         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0);
 453         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
 454         udelay(2); /* delay at least 1200 ns */
 455         setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1);
 456         udelay(1); /* delay at least 120 ns */
 457         setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2);
 458         setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE);
 459 #endif
 460 }
 461
 462 static void sunxi_lcdc_panel_enable(void)
 463 {
 464         int pin;
 465
 466         /*
 467          * Start with backlight disabled to avoid the screen flashing to
 468          * white while the lcd inits.
 469          */
 470         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 471         if (pin != -1) {
 472                 gpio_request(pin, "lcd_backlight_enable");
 473                 gpio_direction_output(pin, 0);
 474         }
 475
 476         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 477         if (pin != -1) {
 478                 gpio_request(pin, "lcd_backlight_pwm");
 479                 /* backlight pwm is inverted, set to 1 to disable backlight */
 480                 gpio_direction_output(pin, 1);
 481         }
 482
 483         /* Give the backlight some time to turn off and power up the panel. */
 484         mdelay(40);
 485         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
 486         if (pin != -1) {
 487                 gpio_request(pin, "lcd_power");
 488                 gpio_direction_output(pin, 1);
 489         }
 490 }
 491
 492 static void sunxi_lcdc_backlight_enable(void)
 493 {
 494         int pin;
 495
 496         /*
 497          * We want to have scanned out at least one frame before enabling the
 498          * backlight to avoid the screen flashing to white when we enable it.
 499          */
 500         mdelay(40);
 501
 502         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 503         if (pin != -1)
 504                 gpio_direction_output(pin, 1);
 505
 506         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 507         if (pin != -1) {
 508                 /* backlight pwm is inverted, set to 0 to enable backlight */
 509                 gpio_direction_output(pin, 0);
 510         }
 511 }
 512
 513 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
 514 {
 515         int delay;
 516
 517         delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
 518         return (delay > 30) ? 30 : delay;
 519 }
 520
 521 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 522 {
 523         struct sunxi_lcdc_reg * const lcdc =
 524                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 525         int bp, clk_delay, clk_div, clk_double, pin, total, val;
 526
 527         for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 528 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 529                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
 530 #endif
 531 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 532                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LVDS0);
 533 #endif
 534
 535         sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 536
 537         /* Use tcon0 */
 538         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 539                         SUNXI_LCDC_CTRL_IO_MAP_TCON0);
 540
 541         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 542         writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
 543                SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
 544
 545         writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
 546                SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
 547
 548         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 549                &lcdc->tcon0_timing_active);
 550
 551         bp = mode->hsync_len + mode->left_margin;
 552         total = mode->xres + mode->right_margin + bp;
 553         writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
 554                SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
 555
 556         bp = mode->vsync_len + mode->upper_margin;
 557         total = mode->yres + mode->lower_margin + bp;
 558         writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
 559                SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
 560
 561 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 562         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 563                &lcdc->tcon0_timing_sync);
 564
 565         writel(0, &lcdc->tcon0_hv_intf);
 566         writel(0, &lcdc->tcon0_cpu_intf);
 567 #endif
 568 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 569         val = (sunxi_display.depth == 18) ? 1 : 0;
 570         writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val), &lcdc->tcon0_lvds_intf);
 571 #endif
 572
 573         if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
 574                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
 575                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
 576                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
 577                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
 578                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
 579                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
 580                 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
 581                 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
 582                 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
 583                 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
 584                 writel(((sunxi_display.depth == 18) ?
 585                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
 586                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
 587                        &lcdc->tcon0_frm_ctrl);
 588         }
 589
 590 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
 591         val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0;
 592 #endif
 593 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
 594         val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60;
 595 #endif
 596         if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 597                 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 598         if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
 599                 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 600         writel(val, &lcdc->tcon0_io_polarity);
 601
 602         writel(0, &lcdc->tcon0_io_tristate);
 603 }
 604
 605 #if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA
 606 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 607                                       int *clk_div, int *clk_double,
 608                                       bool use_portd_hvsync)
 609 {
 610         struct sunxi_lcdc_reg * const lcdc =
 611                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 612         int bp, clk_delay, total, val;
 613
 614         /* Use tcon1 */
 615         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 616                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 617
 618         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 619         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 620                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl);
 621
 622         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 623                &lcdc->tcon1_timing_source);
 624         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 625                &lcdc->tcon1_timing_scale);
 626         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 627                &lcdc->tcon1_timing_out);
 628
 629         bp = mode->hsync_len + mode->left_margin;
 630         total = mode->xres + mode->right_margin + bp;
 631         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 632                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 633
 634         bp = mode->vsync_len + mode->upper_margin;
 635         total = mode->yres + mode->lower_margin + bp;
 636         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 637                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 638
 639         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 640                &lcdc->tcon1_timing_sync);
 641
 642         if (use_portd_hvsync) {
 643                 sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD0_LCD0);
 644                 sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD0_LCD0);
 645
 646                 val = 0;
 647                 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 648                         val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 649                 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 650                         val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 651                 writel(val, &lcdc->tcon1_io_polarity);
 652
 653                 clrbits_le32(&lcdc->tcon1_io_tristate,
 654                              SUNXI_LCDC_TCON_VSYNC_MASK |
 655                              SUNXI_LCDC_TCON_HSYNC_MASK);
 656         }
 657         sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 658 }
 659 #endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA */
 660
 661 #ifdef CONFIG_VIDEO_HDMI
 662
 663 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 664 {
 665         struct sunxi_hdmi_reg * const hdmi =
 666                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 667         u8 checksum = 0;
 668         u8 avi_info_frame[17] = {
 669                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 670                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 671                 0x00
 672         };
 673         u8 vendor_info_frame[19] = {
 674                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 675                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 676                 0x00, 0x00, 0x00
 677         };
 678         int i;
 679
 680         if (mode->pixclock_khz <= 27000)
 681                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 682         else
 683                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 684
 685         if (mode->xres * 100 / mode->yres < 156)
 686                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 687         else
 688                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 689
 690         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 691                 checksum += avi_info_frame[i];
 692
 693         avi_info_frame[3] = 0x100 - checksum;
 694
 695         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 696                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 697
 698         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 699         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 700
 701         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 702                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 703
 704         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 705         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 706
 707         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 708 }
 709
 710 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 711                                 int clk_div, int clk_double)
 712 {
 713         struct sunxi_hdmi_reg * const hdmi =
 714                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 715         int x, y;
 716
 717         /* Write clear interrupt status bits */
 718         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 719
 720         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 721                 sunxi_hdmi_setup_info_frames(mode);
 722
 723         /* Set input sync enable */
 724         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 725
 726         /* Init various registers, select pll3 as clock source */
 727         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 728         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 729         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 730         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 731         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 732
 733         /* Setup clk div and doubler */
 734         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 735                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 736         if (!clk_double)
 737                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 738
 739         /* Setup timing registers */
 740         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 741                &hdmi->video_size);
 742
 743         x = mode->hsync_len + mode->left_margin;
 744         y = mode->vsync_len + mode->upper_margin;
 745         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 746
 747         x = mode->right_margin;
 748         y = mode->lower_margin;
 749         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 750
 751         x = mode->hsync_len;
 752         y = mode->vsync_len;
 753         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 754
 755         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 756                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 757
 758         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 759                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 760 }
 761
 762 static void sunxi_hdmi_enable(void)
 763 {
 764         struct sunxi_hdmi_reg * const hdmi =
 765                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 766
 767         udelay(100);
 768         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 769 }
 770
 771 #endif /* CONFIG_VIDEO_HDMI */
 772
 773 #ifdef CONFIG_VIDEO_VGA
 774
 775 static void sunxi_vga_mode_set(void)
 776 {
 777         struct sunxi_ccm_reg * const ccm =
 778                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 779         struct sunxi_tve_reg * const tve =
 780                 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
 781
 782         /* Clock on */
 783         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
 784
 785         /* Set TVE in VGA mode */
 786         writel(SUNXI_TVE_GCTRL_DAC_INPUT(0, 1) |
 787                SUNXI_TVE_GCTRL_DAC_INPUT(1, 2) |
 788                SUNXI_TVE_GCTRL_DAC_INPUT(2, 3), &tve->gctrl);
 789         writel(SUNXI_TVE_GCTRL_CFG0_VGA, &tve->cfg0);
 790         writel(SUNXI_TVE_GCTRL_DAC_CFG0_VGA, &tve->dac_cfg0);
 791         writel(SUNXI_TVE_GCTRL_UNKNOWN1_VGA, &tve->unknown1);
 792 }
 793
 794 static void sunxi_vga_enable(void)
 795 {
 796         struct sunxi_tve_reg * const tve =
 797                 (struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
 798
 799         setbits_le32(&tve->gctrl, SUNXI_TVE_GCTRL_ENABLE);
 800 }
 801
 802 #endif /* CONFIG_VIDEO_VGA */
 803
 804 static void sunxi_drc_init(void)
 805 {
 806 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
 807         struct sunxi_ccm_reg * const ccm =
 808                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 809
 810         /* On sun6i the drc must be clocked even when in pass-through mode */
 811         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 812         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 813 #endif
 814 }
 815
 816 #ifdef CONFIG_VIDEO_VGA_VIA_LCD
 817 static void sunxi_vga_external_dac_enable(void)
 818 {
 819         int pin;
 820
 821         pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
 822         if (pin != -1) {
 823                 gpio_request(pin, "vga_enable");
 824                 gpio_direction_output(pin, 1);
 825         }
 826 }
 827 #endif /* CONFIG_VIDEO_VGA_VIA_LCD */
 828
 829 static void sunxi_engines_init(void)
 830 {
 831         sunxi_composer_init();
 832         sunxi_lcdc_init();
 833         sunxi_drc_init();
 834 }
 835
 836 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 837                            unsigned int address)
 838 {
 839         int __maybe_unused clk_div, clk_double;
 840
 841         switch (sunxi_display.monitor) {
 842         case sunxi_monitor_none:
 843                 break;
 844         case sunxi_monitor_dvi:
 845         case sunxi_monitor_hdmi:
 846 #ifdef CONFIG_VIDEO_HDMI
 847                 sunxi_composer_mode_set(mode, address);
 848                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0);
 849                 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 850                 sunxi_composer_enable();
 851                 sunxi_lcdc_enable();
 852                 sunxi_hdmi_enable();
 853 #endif
 854                 break;
 855         case sunxi_monitor_lcd:
 856                 sunxi_lcdc_panel_enable();
 857                 sunxi_composer_mode_set(mode, address);
 858                 sunxi_lcdc_tcon0_mode_set(mode);
 859                 sunxi_composer_enable();
 860                 sunxi_lcdc_enable();
 861                 sunxi_lcdc_backlight_enable();
 862                 break;
 863         case sunxi_monitor_vga:
 864 #ifdef CONFIG_VIDEO_VGA
 865                 sunxi_composer_mode_set(mode, address);
 866                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1);
 867                 sunxi_vga_mode_set();
 868                 sunxi_composer_enable();
 869                 sunxi_lcdc_enable();
 870                 sunxi_vga_enable();
 871 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 872                 sunxi_composer_mode_set(mode, address);
 873                 sunxi_lcdc_tcon0_mode_set(mode);
 874                 sunxi_composer_enable();
 875                 sunxi_lcdc_enable();
 876                 sunxi_vga_external_dac_enable();
 877 #endif
 878                 break;
 879         }
 880 }
 881
 882 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 883 {
 884         switch (monitor) {
 885         case sunxi_monitor_none:        return "none";
 886         case sunxi_monitor_dvi:         return "dvi";
 887         case sunxi_monitor_hdmi:        return "hdmi";
 888         case sunxi_monitor_lcd:         return "lcd";
 889         case sunxi_monitor_vga:         return "vga";
 890         }
 891         return NULL; /* never reached */
 892 }
 893
 894 void *video_hw_init(void)
 895 {
 896         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 897         const struct ctfb_res_modes *mode;
 898         struct ctfb_res_modes custom;
 899         const char *options;
 900 #ifdef CONFIG_VIDEO_HDMI
 901         int ret, hpd, hpd_delay, edid;
 902 #endif
 903         char mon[16];
 904         char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
 905         int i;
 906
 907         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 908
 909         printf("Reserved %dkB of RAM for Framebuffer.\n",
 910                CONFIG_SUNXI_FB_SIZE >> 10);
 911         gd->fb_base = gd->ram_top;
 912
 913         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 914                                  &sunxi_display.depth, &options);
 915 #ifdef CONFIG_VIDEO_HDMI
 916         hpd = video_get_option_int(options, "hpd", 1);
 917         hpd_delay = video_get_option_int(options, "hpd_delay", 500);
 918         edid = video_get_option_int(options, "edid", 1);
 919         sunxi_display.monitor = sunxi_monitor_dvi;
 920 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
 921         sunxi_display.monitor = sunxi_monitor_vga;
 922 #else
 923         sunxi_display.monitor = sunxi_monitor_lcd;
 924 #endif
 925         video_get_option_string(options, "monitor", mon, sizeof(mon),
 926                                 sunxi_get_mon_desc(sunxi_display.monitor));
 927         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 928                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 929                         sunxi_display.monitor = i;
 930                         break;
 931                 }
 932         }
 933         if (i > SUNXI_MONITOR_LAST)
 934                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 935                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 936
 937 #ifdef CONFIG_VIDEO_HDMI
 938         /* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
 939         if (sunxi_display.monitor == sunxi_monitor_dvi ||
 940             sunxi_display.monitor == sunxi_monitor_hdmi) {
 941                 /* Always call hdp_detect, as it also enables clocks, etc. */
 942                 ret = sunxi_hdmi_hpd_detect(hpd_delay);
 943                 if (ret) {
 944                         printf("HDMI connected: ");
 945                         if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
 946                                 mode = &custom;
 947                 } else if (hpd) {
 948                         sunxi_hdmi_shutdown();
 949                         /* Fallback to lcd / vga / none */
 950                         if (lcd_mode[0]) {
 951                                 sunxi_display.monitor = sunxi_monitor_lcd;
 952                         } else {
 953 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
 954                                 sunxi_display.monitor = sunxi_monitor_vga;
 955 #else
 956                                 sunxi_display.monitor = sunxi_monitor_none;
 957 #endif
 958                         }
 959                 } /* else continue with hdmi/dvi without a cable connected */
 960         }
 961 #endif
 962
 963         switch (sunxi_display.monitor) {
 964         case sunxi_monitor_none:
 965                 return NULL;
 966         case sunxi_monitor_dvi:
 967         case sunxi_monitor_hdmi:
 968 #ifdef CONFIG_VIDEO_HDMI
 969                 break;
 970 #else
 971                 printf("HDMI/DVI not supported on this board\n");
 972                 sunxi_display.monitor = sunxi_monitor_none;
 973                 return NULL;
 974 #endif
 975         case sunxi_monitor_lcd:
 976                 if (lcd_mode[0]) {
 977                         sunxi_display.depth = video_get_params(&custom, lcd_mode);
 978                         mode = &custom;
 979                         break;
 980                 }
 981                 printf("LCD not supported on this board\n");
 982                 sunxi_display.monitor = sunxi_monitor_none;
 983                 return NULL;
 984         case sunxi_monitor_vga:
 985 #if defined CONFIG_VIDEO_VGA_VIA_LCD || defined CONFIG_VIDEO_VGA
 986                 sunxi_display.depth = 18;
 987                 break;
 988 #else
 989                 printf("VGA not supported on this board\n");
 990                 sunxi_display.monitor = sunxi_monitor_none;
 991                 return NULL;
 992 #endif
 993         }
 994
 995         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 996                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 997                 mode = &res_mode_init[RES_MODE_1024x768];
 998         } else {
 999                 printf("Setting up a %dx%d %s console\n", mode->xres,
1000                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
1001         }
1002
1003         sunxi_engines_init();
1004         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
1005
1006         /*
1007          * These are the only members of this structure that are used. All the
1008          * others are driver specific. There is nothing to decribe pitch or
1009          * stride, but we are lucky with our hw.
1010          */
1011         graphic_device->frameAdrs = gd->fb_base;
1012         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
1013         graphic_device->gdfBytesPP = 4;
1014         graphic_device->winSizeX = mode->xres;
1015         graphic_device->winSizeY = mode->yres;
1016
1017         return graphic_device;
1018 }
1019
1020 /*
1021  * Simplefb support.
1022  */
1023 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
1024 int sunxi_simplefb_setup(void *blob)
1025 {
1026         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
1027         int offset, ret;
1028         const char *pipeline = NULL;
1029
1030         switch (sunxi_display.monitor) {
1031         case sunxi_monitor_none:
1032                 return 0;
1033         case sunxi_monitor_dvi:
1034         case sunxi_monitor_hdmi:
1035                 pipeline = "de_be0-lcd0-hdmi";
1036                 break;
1037         case sunxi_monitor_lcd:
1038                 pipeline = "de_be0-lcd0";
1039                 break;
1040         case sunxi_monitor_vga:
1041 #ifdef CONFIG_VIDEO_VGA
1042                 pipeline = "de_be0-lcd0-tve0";
1043 #elif defined CONFIG_VIDEO_VGA_VIA_LCD
1044                 pipeline = "de_be0-lcd0";
1045 #endif
1046                 break;
1047         }
1048
1049         /* Find a prefilled simpefb node, matching out pipeline config */
1050         offset = fdt_node_offset_by_compatible(blob, -1,
1051                                                "allwinner,simple-framebuffer");
1052         while (offset >= 0) {
1053                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
1054                                       pipeline);
1055                 if (ret == 0)
1056                         break;
1057                 offset = fdt_node_offset_by_compatible(blob, offset,
1058                                                "allwinner,simple-framebuffer");
1059         }
1060         if (offset < 0) {
1061                 eprintf("Cannot setup simplefb: node not found\n");
1062                 return 0; /* Keep older kernels working */
1063         }
1064
1065         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
1066                         graphic_device->winSizeX, graphic_device->winSizeY,
1067                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
1068                         "x8r8g8b8");
1069         if (ret)
1070                 eprintf("Cannot setup simplefb: Error setting properties\n");
1071
1072         return ret;
1073 }
1074 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */