2 * Display driver for Allwinner SoCs.
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/display.h>
14 #include <asm/global_data.h>
17 #include <fdt_support.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct sunxi_display {
24 GraphicDevice graphic_device;
28 static int sunxi_hdmi_hpd_detect(void)
30 struct sunxi_ccm_reg * const ccm =
31 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
32 struct sunxi_hdmi_reg * const hdmi =
33 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
35 /* Set pll3 to 300MHz */
36 clock_set_pll3(300000000);
38 /* Set hdmi parent to pll3 */
39 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
42 /* Set ahb gating to pass */
43 #ifdef CONFIG_MACH_SUN6I
44 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
46 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
49 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
51 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
52 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
56 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
59 /* No need to keep these running */
60 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
61 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
62 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
63 #ifdef CONFIG_MACH_SUN6I
64 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
72 * This is the entity that mixes and matches the different layers and inputs.
73 * Allwinner calls it the back-end, but i like composer better.
75 static void sunxi_composer_init(void)
77 struct sunxi_ccm_reg * const ccm =
78 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
79 struct sunxi_de_be_reg * const de_be =
80 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
83 #ifdef CONFIG_MACH_SUN6I
85 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
89 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
90 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
91 clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
93 /* Engine bug, clear registers after reset */
94 for (i = 0x0800; i < 0x1000; i += 4)
95 writel(0, SUNXI_DE_BE0_BASE + i);
97 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
100 static void sunxi_composer_mode_set(struct fb_videomode *mode,
101 unsigned int address)
103 struct sunxi_de_be_reg * const de_be =
104 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
106 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
108 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
109 &de_be->layer0_size);
110 writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
111 writel(address << 3, &de_be->layer0_addr_low32b);
112 writel(address >> 29, &de_be->layer0_addr_high4b);
113 writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
115 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
119 * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
121 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
123 struct sunxi_ccm_reg * const ccm =
124 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
125 int value, n, m, diff;
126 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
130 * Find the lowest divider resulting in a matching clock, if there
131 * is no match, pick the closest lower clock, as monitors tend to
132 * not sync to higher frequencies.
134 for (m = 15; m > 0; m--) {
135 n = (m * dotclock) / 3000;
137 if ((n >= 9) && (n <= 127)) {
138 value = (3000 * n) / m;
139 diff = dotclock - value;
140 if (diff < best_diff) {
148 /* These are just duplicates */
152 n = (m * dotclock) / 6000;
153 if ((n >= 9) && (n <= 127)) {
154 value = (6000 * n) / m;
155 diff = dotclock - value;
156 if (diff < best_diff) {
165 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
166 dotclock, (best_double + 1) * 3000 * best_n / best_m,
167 best_double + 1, best_n, best_m);
169 clock_set_pll3(best_n * 3000000);
171 writel(CCM_LCD_CH1_CTRL_GATE |
172 (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
173 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
176 *clk_double = best_double;
179 static void sunxi_lcdc_init(void)
181 struct sunxi_ccm_reg * const ccm =
182 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
183 struct sunxi_lcdc_reg * const lcdc =
184 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
187 #ifdef CONFIG_MACH_SUN6I
188 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
190 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
194 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
197 writel(0, &lcdc->ctrl); /* Disable tcon */
198 writel(0, &lcdc->int0); /* Disable all interrupts */
200 /* Disable tcon0 dot clock */
201 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
203 /* Set all io lines to tristate */
204 writel(0xffffffff, &lcdc->tcon0_io_tristate);
205 writel(0xffffffff, &lcdc->tcon1_io_tristate);
208 static void sunxi_lcdc_mode_set(struct fb_videomode *mode,
209 int *clk_div, int *clk_double)
211 struct sunxi_lcdc_reg * const lcdc =
212 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
216 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
217 SUNXI_LCDC_CTRL_IO_MAP_TCON1);
219 /* Enabled, 0x1e start delay */
220 writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
221 SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
223 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
224 &lcdc->tcon1_timing_source);
225 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
226 &lcdc->tcon1_timing_scale);
227 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
228 &lcdc->tcon1_timing_out);
230 bp = mode->hsync_len + mode->left_margin;
231 total = mode->xres + mode->right_margin + bp;
232 writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
233 SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
235 bp = mode->vsync_len + mode->upper_margin;
236 total = mode->yres + mode->lower_margin + bp;
237 writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
238 SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
240 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
241 &lcdc->tcon1_timing_sync);
243 sunxi_lcdc_pll_set(mode->pixclock, clk_div, clk_double);
246 #ifdef CONFIG_MACH_SUN6I
247 static void sunxi_drc_init(void)
249 struct sunxi_ccm_reg * const ccm =
250 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
252 /* On sun6i the drc must be clocked even when in pass-through mode */
253 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
254 clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
258 static void sunxi_hdmi_mode_set(struct fb_videomode *mode,
259 int clk_div, int clk_double)
261 struct sunxi_hdmi_reg * const hdmi =
262 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
265 /* Write clear interrupt status bits */
266 writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
268 /* Init various registers, select pll3 as clock source */
269 writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
270 writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
271 writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
272 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
273 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
275 /* Setup clk div and doubler */
276 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
277 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
279 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
281 /* Setup timing registers */
282 writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
285 x = mode->hsync_len + mode->left_margin;
286 y = mode->vsync_len + mode->upper_margin;
287 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
289 x = mode->right_margin;
290 y = mode->lower_margin;
291 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
295 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
297 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
298 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
300 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
301 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
304 static void sunxi_engines_init(void)
306 sunxi_composer_init();
308 #ifdef CONFIG_MACH_SUN6I
313 static void sunxi_mode_set(struct fb_videomode *mode, unsigned int address)
315 struct sunxi_de_be_reg * const de_be =
316 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
317 struct sunxi_lcdc_reg * const lcdc =
318 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
319 struct sunxi_hdmi_reg * const hdmi =
320 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
321 int clk_div, clk_double;
325 clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
326 clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
327 clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
329 sunxi_composer_mode_set(mode, address);
330 sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
331 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
333 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
334 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
336 udelay(1000000 / mode->refresh + 500);
338 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
340 udelay(1000000 / mode->refresh + 500);
342 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
344 udelay(1000000 / mode->refresh + 500);
347 * Sometimes the display pipeline does not sync up properly, if
348 * this happens the hdmi fifo underrun or overrun bits are set.
350 if (readl(&hdmi->irq) &
351 (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
354 printf("HDMI fifo under or overrun\n");
358 void *video_hw_init(void)
360 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
362 * Vesa standard 1024x768@60
363 * 65.0 1024 1048 1184 1344 768 771 777 806 -hsync -vsync
365 struct fb_videomode mode = {
383 memset(&sunxi_display, 0, sizeof(struct sunxi_display));
385 printf("Reserved %dkB of RAM for Framebuffer.\n",
386 CONFIG_SUNXI_FB_SIZE >> 10);
387 gd->fb_base = gd->ram_top;
389 ret = sunxi_hdmi_hpd_detect();
393 printf("HDMI connected.\n");
394 sunxi_display.enabled = true;
396 printf("Setting up a %s console.\n", mode.name);
397 sunxi_engines_init();
398 sunxi_mode_set(&mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
401 * These are the only members of this structure that are used. All the
402 * others are driver specific. There is nothing to decribe pitch or
403 * stride, but we are lucky with our hw.
405 graphic_device->frameAdrs = gd->fb_base;
406 graphic_device->gdfIndex = GDF_32BIT_X888RGB;
407 graphic_device->gdfBytesPP = 4;
408 graphic_device->winSizeX = mode.xres;
409 graphic_device->winSizeY = mode.yres;
411 return graphic_device;
417 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
418 int sunxi_simplefb_setup(void *blob)
420 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
423 if (!sunxi_display.enabled)
426 /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
427 offset = fdt_node_offset_by_compatible(blob, -1,
428 "allwinner,simple-framebuffer");
429 while (offset >= 0) {
430 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
434 offset = fdt_node_offset_by_compatible(blob, offset,
435 "allwinner,simple-framebuffer");
438 eprintf("Cannot setup simplefb: node not found\n");
439 return 0; /* Keep older kernels working */
442 ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
443 graphic_device->winSizeX, graphic_device->winSizeY,
444 graphic_device->winSizeX * graphic_device->gdfBytesPP,
447 eprintf("Cannot setup simplefb: Error setting properties\n");
451 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */