2 * Display driver for Allwinner SoCs.
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/display.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/global_data.h>
20 #include <fdt_support.h>
22 #include "videomodes.h"
24 DECLARE_GLOBAL_DATA_PTR;
33 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
35 struct sunxi_display {
36 GraphicDevice graphic_device;
38 enum sunxi_monitor monitor;
42 #ifdef CONFIG_VIDEO_HDMI
45 * Wait up to 200ms for value to be set in given part of reg.
47 static int await_completion(u32 *reg, u32 mask, u32 val)
49 unsigned long tmo = timer_get_us() + 200000;
51 while ((readl(reg) & mask) != val) {
52 if (timer_get_us() > tmo) {
53 printf("DDC: timeout reading EDID\n");
60 static int sunxi_hdmi_hpd_detect(void)
62 struct sunxi_ccm_reg * const ccm =
63 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
64 struct sunxi_hdmi_reg * const hdmi =
65 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
66 unsigned long tmo = timer_get_us() + 300000;
68 /* Set pll3 to 300MHz */
69 clock_set_pll3(300000000);
71 /* Set hdmi parent to pll3 */
72 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
75 /* Set ahb gating to pass */
76 #ifdef CONFIG_MACH_SUN6I
77 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
79 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
82 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
84 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
85 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
87 while (timer_get_us() < tmo) {
88 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
95 static void sunxi_hdmi_shutdown(void)
97 struct sunxi_ccm_reg * const ccm =
98 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
99 struct sunxi_hdmi_reg * const hdmi =
100 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
102 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
103 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
104 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
105 #ifdef CONFIG_MACH_SUN6I
106 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
111 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
113 struct sunxi_hdmi_reg * const hdmi =
114 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
116 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
117 writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
118 SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
119 SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
120 SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
121 #ifndef CONFIG_MACH_SUN6I
122 writel(n, &hdmi->ddc_byte_count);
123 writel(cmnd, &hdmi->ddc_cmnd);
125 writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
127 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
129 return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
132 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
134 struct sunxi_hdmi_reg * const hdmi =
135 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
144 if (sunxi_hdmi_ddc_do_command(
145 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
149 for (i = 0; i < n; i++)
150 *buf++ = readb(&hdmi->ddc_fifo_data);
159 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
164 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
167 r = edid_check_checksum(buf);
169 printf("EDID block %d: checksum error%s\n",
170 block, retries ? ", retrying" : "");
172 } while (r && retries--);
177 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
179 struct edid1_info edid1;
180 struct edid_cea861_info cea681[4];
181 struct edid_detailed_timing *t =
182 (struct edid_detailed_timing *)edid1.monitor_details.timing;
183 struct sunxi_hdmi_reg * const hdmi =
184 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
185 struct sunxi_ccm_reg * const ccm =
186 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
187 int i, r, ext_blocks = 0;
189 /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
190 writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
192 writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
194 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
196 /* Reset i2c controller */
197 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
198 writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
199 SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
200 SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
201 SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
202 if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
205 writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
206 #ifndef CONFIG_MACH_SUN6I
207 writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
208 SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
211 r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
213 r = edid_check_info(&edid1);
215 printf("EDID: invalid EDID data\n");
220 ext_blocks = edid1.extension_flag;
223 for (i = 0; i < ext_blocks; i++) {
224 if (sunxi_hdmi_edid_get_block(1 + i,
225 (u8 *)&cea681[i]) != 0) {
232 /* Disable DDC engine, no longer needed */
233 clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
234 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
239 /* We want version 1.3 or 1.2 with detailed timing info */
240 if (edid1.version != 1 || (edid1.revision < 3 &&
241 !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
242 printf("EDID: unsupported version %d.%d\n",
243 edid1.version, edid1.revision);
247 /* Take the first usable detailed timing */
248 for (i = 0; i < 4; i++, t++) {
249 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
254 printf("EDID: no usable detailed timing found\n");
258 /* Check for basic audio support, if found enable hdmi output */
259 sunxi_display.monitor = sunxi_monitor_dvi;
260 for (i = 0; i < ext_blocks; i++) {
261 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
262 cea681[i].revision < 2)
265 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
266 sunxi_display.monitor = sunxi_monitor_hdmi;
272 #endif /* CONFIG_VIDEO_HDMI */
275 * This is the entity that mixes and matches the different layers and inputs.
276 * Allwinner calls it the back-end, but i like composer better.
278 static void sunxi_composer_init(void)
280 struct sunxi_ccm_reg * const ccm =
281 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
282 struct sunxi_de_be_reg * const de_be =
283 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
286 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
288 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
292 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
293 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
294 clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
296 /* Engine bug, clear registers after reset */
297 for (i = 0x0800; i < 0x1000; i += 4)
298 writel(0, SUNXI_DE_BE0_BASE + i);
300 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
303 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
304 unsigned int address)
306 struct sunxi_de_be_reg * const de_be =
307 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
309 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
311 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
312 &de_be->layer0_size);
313 writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
314 writel(address << 3, &de_be->layer0_addr_low32b);
315 writel(address >> 29, &de_be->layer0_addr_high4b);
316 writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
318 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
321 static void sunxi_composer_enable(void)
323 struct sunxi_de_be_reg * const de_be =
324 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
326 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
327 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
331 * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
333 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
334 int *clk_div, int *clk_double)
336 struct sunxi_ccm_reg * const ccm =
337 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
338 int value, n, m, min_m, max_m, diff;
339 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
351 * Find the lowest divider resulting in a matching clock, if there
352 * is no match, pick the closest lower clock, as monitors tend to
353 * not sync to higher frequencies.
355 for (m = min_m; m <= max_m; m++) {
356 n = (m * dotclock) / 3000;
358 if ((n >= 9) && (n <= 127)) {
359 value = (3000 * n) / m;
360 diff = dotclock - value;
361 if (diff < best_diff) {
369 /* These are just duplicates */
373 n = (m * dotclock) / 6000;
374 if ((n >= 9) && (n <= 127)) {
375 value = (6000 * n) / m;
376 diff = dotclock - value;
377 if (diff < best_diff) {
386 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
387 dotclock, (best_double + 1) * 3000 * best_n / best_m,
388 best_double + 1, best_n, best_m);
390 clock_set_pll3(best_n * 3000000);
393 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
394 (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
395 CCM_LCD_CH0_CTRL_PLL3),
396 &ccm->lcd0_ch0_clk_cfg);
398 writel(CCM_LCD_CH1_CTRL_GATE |
399 (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
400 CCM_LCD_CH1_CTRL_PLL3) |
401 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
405 *clk_double = best_double;
408 static void sunxi_lcdc_init(void)
410 struct sunxi_ccm_reg * const ccm =
411 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
412 struct sunxi_lcdc_reg * const lcdc =
413 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
416 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
417 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
419 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
423 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
426 writel(0, &lcdc->ctrl); /* Disable tcon */
427 writel(0, &lcdc->int0); /* Disable all interrupts */
429 /* Disable tcon0 dot clock */
430 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
432 /* Set all io lines to tristate */
433 writel(0xffffffff, &lcdc->tcon0_io_tristate);
434 writel(0xffffffff, &lcdc->tcon1_io_tristate);
437 static void sunxi_lcdc_enable(void)
439 struct sunxi_lcdc_reg * const lcdc =
440 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
442 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
445 static void sunxi_lcdc_panel_enable(void)
450 * Start with backlight disabled to avoid the screen flashing to
451 * white while the lcd inits.
453 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
455 gpio_request(pin, "lcd_backlight_enable");
456 gpio_direction_output(pin, 0);
459 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
461 gpio_request(pin, "lcd_backlight_pwm");
462 /* backlight pwm is inverted, set to 1 to disable backlight */
463 gpio_direction_output(pin, 1);
466 /* Give the backlight some time to turn off and power up the panel. */
468 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
470 gpio_request(pin, "lcd_power");
471 gpio_direction_output(pin, 1);
475 static void sunxi_lcdc_backlight_enable(void)
480 * We want to have scanned out at least one frame before enabling the
481 * backlight to avoid the screen flashing to white when we enable it.
485 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
487 gpio_direction_output(pin, 1);
489 pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
491 /* backlight pwm is inverted, set to 0 to enable backlight */
492 gpio_direction_output(pin, 0);
496 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
500 delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
501 return (delay > 30) ? 30 : delay;
504 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
506 struct sunxi_lcdc_reg * const lcdc =
507 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
508 int bp, clk_delay, clk_div, clk_double, pin, total, val;
510 for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
511 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
513 sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
516 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
517 SUNXI_LCDC_CTRL_IO_MAP_TCON0);
519 clk_delay = sunxi_lcdc_get_clk_delay(mode);
520 writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
521 SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
523 writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
524 SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
526 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
527 &lcdc->tcon0_timing_active);
529 bp = mode->hsync_len + mode->left_margin;
530 total = mode->xres + mode->right_margin + bp;
531 writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
532 SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
534 bp = mode->vsync_len + mode->upper_margin;
535 total = mode->yres + mode->lower_margin + bp;
536 writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
537 SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
539 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
540 &lcdc->tcon0_timing_sync);
542 /* We only support hv-sync parallel lcd-s for now */
543 writel(0, &lcdc->tcon0_hv_intf);
544 writel(0, &lcdc->tcon0_cpu_intf);
546 if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
547 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
548 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
549 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
550 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
551 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
552 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
553 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
554 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
555 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
556 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
557 writel(((sunxi_display.depth == 18) ?
558 SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
559 SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
560 &lcdc->tcon0_frm_ctrl);
564 if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
565 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
566 if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
567 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
568 writel(val, &lcdc->tcon0_io_polarity);
570 writel(0, &lcdc->tcon0_io_tristate);
573 #ifdef CONFIG_VIDEO_HDMI
575 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
576 int *clk_div, int *clk_double)
578 struct sunxi_lcdc_reg * const lcdc =
579 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
583 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
584 SUNXI_LCDC_CTRL_IO_MAP_TCON1);
586 /* Enabled, 0x1e start delay */
587 writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
588 SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
590 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
591 &lcdc->tcon1_timing_source);
592 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
593 &lcdc->tcon1_timing_scale);
594 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
595 &lcdc->tcon1_timing_out);
597 bp = mode->hsync_len + mode->left_margin;
598 total = mode->xres + mode->right_margin + bp;
599 writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
600 SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
602 bp = mode->vsync_len + mode->upper_margin;
603 total = mode->yres + mode->lower_margin + bp;
604 writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
605 SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
607 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
608 &lcdc->tcon1_timing_sync);
610 sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
613 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
615 struct sunxi_hdmi_reg * const hdmi =
616 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
618 u8 avi_info_frame[17] = {
619 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
620 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
623 u8 vendor_info_frame[19] = {
624 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
625 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
630 if (mode->pixclock_khz <= 27000)
631 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
633 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
635 if (mode->xres * 100 / mode->yres < 156)
636 avi_info_frame[5] |= 0x18; /* 4 : 3 */
638 avi_info_frame[5] |= 0x28; /* 16 : 9 */
640 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
641 checksum += avi_info_frame[i];
643 avi_info_frame[3] = 0x100 - checksum;
645 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
646 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
648 writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
649 writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
651 for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
652 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
654 writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
655 writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
657 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
660 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
661 int clk_div, int clk_double)
663 struct sunxi_hdmi_reg * const hdmi =
664 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
667 /* Write clear interrupt status bits */
668 writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
670 if (sunxi_display.monitor == sunxi_monitor_hdmi)
671 sunxi_hdmi_setup_info_frames(mode);
673 /* Set input sync enable */
674 writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
676 /* Init various registers, select pll3 as clock source */
677 writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
678 writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
679 writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
680 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
681 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
683 /* Setup clk div and doubler */
684 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
685 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
687 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
689 /* Setup timing registers */
690 writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
693 x = mode->hsync_len + mode->left_margin;
694 y = mode->vsync_len + mode->upper_margin;
695 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
697 x = mode->right_margin;
698 y = mode->lower_margin;
699 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
703 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
705 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
706 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
708 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
709 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
712 static void sunxi_hdmi_enable(void)
714 struct sunxi_hdmi_reg * const hdmi =
715 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
718 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
721 #endif /* CONFIG_VIDEO_HDMI */
723 static void sunxi_drc_init(void)
725 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
726 struct sunxi_ccm_reg * const ccm =
727 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
729 /* On sun6i the drc must be clocked even when in pass-through mode */
730 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
731 clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
735 static void sunxi_engines_init(void)
737 sunxi_composer_init();
742 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
743 unsigned int address)
745 switch (sunxi_display.monitor) {
746 case sunxi_monitor_none:
748 case sunxi_monitor_dvi:
749 case sunxi_monitor_hdmi: {
750 #ifdef CONFIG_VIDEO_HDMI
751 int clk_div, clk_double;
752 sunxi_composer_mode_set(mode, address);
753 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double);
754 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
755 sunxi_composer_enable();
761 case sunxi_monitor_lcd:
762 sunxi_lcdc_panel_enable();
763 sunxi_composer_mode_set(mode, address);
764 sunxi_lcdc_tcon0_mode_set(mode);
765 sunxi_composer_enable();
767 sunxi_lcdc_backlight_enable();
769 case sunxi_monitor_vga:
774 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
777 case sunxi_monitor_none: return "none";
778 case sunxi_monitor_dvi: return "dvi";
779 case sunxi_monitor_hdmi: return "hdmi";
780 case sunxi_monitor_lcd: return "lcd";
781 case sunxi_monitor_vga: return "vga";
783 return NULL; /* never reached */
786 void *video_hw_init(void)
788 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
789 const struct ctfb_res_modes *mode;
790 struct ctfb_res_modes custom;
792 #ifdef CONFIG_VIDEO_HDMI
796 char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
799 memset(&sunxi_display, 0, sizeof(struct sunxi_display));
801 printf("Reserved %dkB of RAM for Framebuffer.\n",
802 CONFIG_SUNXI_FB_SIZE >> 10);
803 gd->fb_base = gd->ram_top;
805 video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
806 &sunxi_display.depth, &options);
807 #ifdef CONFIG_VIDEO_HDMI
808 hpd = video_get_option_int(options, "hpd", 1);
809 edid = video_get_option_int(options, "edid", 1);
810 sunxi_display.monitor = sunxi_monitor_dvi;
812 sunxi_display.monitor = sunxi_monitor_lcd;
814 video_get_option_string(options, "monitor", mon, sizeof(mon),
815 sunxi_get_mon_desc(sunxi_display.monitor));
816 for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
817 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
818 sunxi_display.monitor = i;
822 if (i > SUNXI_MONITOR_LAST)
823 printf("Unknown monitor: '%s', falling back to '%s'\n",
824 mon, sunxi_get_mon_desc(sunxi_display.monitor));
826 switch (sunxi_display.monitor) {
827 case sunxi_monitor_none:
829 case sunxi_monitor_dvi:
830 case sunxi_monitor_hdmi:
831 #ifndef CONFIG_VIDEO_HDMI
832 printf("HDMI/DVI not supported on this board\n");
835 /* Always call hdp_detect, as it also enables clocks, etc. */
836 ret = sunxi_hdmi_hpd_detect();
838 printf("HDMI connected: ");
839 if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
844 break; /* User has requested to ignore hpd */
846 sunxi_hdmi_shutdown();
848 if (lcd_mode[0] == 0)
849 return NULL; /* No LCD, bail */
851 /* Fall back / through to LCD */
852 sunxi_display.monitor = sunxi_monitor_lcd;
854 case sunxi_monitor_lcd:
856 sunxi_display.depth = video_get_params(&custom, lcd_mode);
860 printf("LCD not supported on this board\n");
862 case sunxi_monitor_vga:
863 printf("VGA not supported on this board\n");
867 if (mode->vmode != FB_VMODE_NONINTERLACED) {
868 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
869 mode = &res_mode_init[RES_MODE_1024x768];
871 printf("Setting up a %dx%d %s console\n", mode->xres,
872 mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
875 sunxi_display.enabled = true;
876 sunxi_engines_init();
877 sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
880 * These are the only members of this structure that are used. All the
881 * others are driver specific. There is nothing to decribe pitch or
882 * stride, but we are lucky with our hw.
884 graphic_device->frameAdrs = gd->fb_base;
885 graphic_device->gdfIndex = GDF_32BIT_X888RGB;
886 graphic_device->gdfBytesPP = 4;
887 graphic_device->winSizeX = mode->xres;
888 graphic_device->winSizeY = mode->yres;
890 return graphic_device;
896 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
897 int sunxi_simplefb_setup(void *blob)
899 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
901 const char *pipeline = NULL;
903 if (!sunxi_display.enabled)
906 switch (sunxi_display.monitor) {
907 case sunxi_monitor_none:
909 case sunxi_monitor_dvi:
910 case sunxi_monitor_hdmi:
911 pipeline = "de_be0-lcd0-hdmi";
913 case sunxi_monitor_lcd:
914 pipeline = "de_be0-lcd0";
916 case sunxi_monitor_vga:
920 /* Find a prefilled simpefb node, matching out pipeline config */
921 offset = fdt_node_offset_by_compatible(blob, -1,
922 "allwinner,simple-framebuffer");
923 while (offset >= 0) {
924 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
928 offset = fdt_node_offset_by_compatible(blob, offset,
929 "allwinner,simple-framebuffer");
932 eprintf("Cannot setup simplefb: node not found\n");
933 return 0; /* Keep older kernels working */
936 ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
937 graphic_device->winSizeX, graphic_device->winSizeY,
938 graphic_device->winSizeX * graphic_device->gdfBytesPP,
941 eprintf("Cannot setup simplefb: Error setting properties\n");
945 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */