2 * Display driver for Allwinner SoCs.
4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clock.h>
13 #include <asm/arch/display.h>
14 #include <asm/global_data.h>
18 #include <fdt_support.h>
20 #include "videomodes.h"
22 DECLARE_GLOBAL_DATA_PTR;
31 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
33 struct sunxi_display {
34 GraphicDevice graphic_device;
36 enum sunxi_monitor monitor;
40 * Wait up to 200ms for value to be set in given part of reg.
42 static int await_completion(u32 *reg, u32 mask, u32 val)
44 unsigned long tmo = timer_get_us() + 200000;
46 while ((readl(reg) & mask) != val) {
47 if (timer_get_us() > tmo) {
48 printf("DDC: timeout reading EDID\n");
55 static int sunxi_hdmi_hpd_detect(void)
57 struct sunxi_ccm_reg * const ccm =
58 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
59 struct sunxi_hdmi_reg * const hdmi =
60 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
61 unsigned long tmo = timer_get_us() + 300000;
63 /* Set pll3 to 300MHz */
64 clock_set_pll3(300000000);
66 /* Set hdmi parent to pll3 */
67 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
70 /* Set ahb gating to pass */
71 #ifdef CONFIG_MACH_SUN6I
72 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
74 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
77 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
79 writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
80 writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
82 while (timer_get_us() < tmo) {
83 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
90 static void sunxi_hdmi_shutdown(void)
92 struct sunxi_ccm_reg * const ccm =
93 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
94 struct sunxi_hdmi_reg * const hdmi =
95 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
97 clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
98 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
99 clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
100 #ifdef CONFIG_MACH_SUN6I
101 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
106 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
108 struct sunxi_hdmi_reg * const hdmi =
109 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
111 setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
112 writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
113 SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
114 SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
115 SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
116 #ifndef CONFIG_MACH_SUN6I
117 writel(n, &hdmi->ddc_byte_count);
118 writel(cmnd, &hdmi->ddc_cmnd);
120 writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
122 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
124 return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
127 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
129 struct sunxi_hdmi_reg * const hdmi =
130 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
139 if (sunxi_hdmi_ddc_do_command(
140 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
144 for (i = 0; i < n; i++)
145 *buf++ = readb(&hdmi->ddc_fifo_data);
154 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
159 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
162 r = edid_check_checksum(buf);
164 printf("EDID block %d: checksum error%s\n",
165 block, retries ? ", retrying" : "");
167 } while (r && retries--);
172 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
174 struct edid1_info edid1;
175 struct edid_cea861_info cea681[4];
176 struct edid_detailed_timing *t =
177 (struct edid_detailed_timing *)edid1.monitor_details.timing;
178 struct sunxi_hdmi_reg * const hdmi =
179 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
180 struct sunxi_ccm_reg * const ccm =
181 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
182 int i, r, ext_blocks = 0;
184 /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
185 writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
187 writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
189 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
191 /* Reset i2c controller */
192 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
193 writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
194 SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
195 SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
196 SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
197 if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
200 writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
201 #ifndef CONFIG_MACH_SUN6I
202 writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
203 SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
206 r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
208 r = edid_check_info(&edid1);
210 printf("EDID: invalid EDID data\n");
215 ext_blocks = edid1.extension_flag;
218 for (i = 0; i < ext_blocks; i++) {
219 if (sunxi_hdmi_edid_get_block(1 + i,
220 (u8 *)&cea681[i]) != 0) {
227 /* Disable DDC engine, no longer needed */
228 clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
229 clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
234 /* We want version 1.3 or 1.2 with detailed timing info */
235 if (edid1.version != 1 || (edid1.revision < 3 &&
236 !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
237 printf("EDID: unsupported version %d.%d\n",
238 edid1.version, edid1.revision);
242 /* Take the first usable detailed timing */
243 for (i = 0; i < 4; i++, t++) {
244 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
249 printf("EDID: no usable detailed timing found\n");
253 /* Check for basic audio support, if found enable hdmi output */
254 sunxi_display.monitor = sunxi_monitor_dvi;
255 for (i = 0; i < ext_blocks; i++) {
256 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
257 cea681[i].revision < 2)
260 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
261 sunxi_display.monitor = sunxi_monitor_hdmi;
268 * This is the entity that mixes and matches the different layers and inputs.
269 * Allwinner calls it the back-end, but i like composer better.
271 static void sunxi_composer_init(void)
273 struct sunxi_ccm_reg * const ccm =
274 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
275 struct sunxi_de_be_reg * const de_be =
276 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
279 #ifdef CONFIG_MACH_SUN6I
281 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
285 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
286 setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
287 clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
289 /* Engine bug, clear registers after reset */
290 for (i = 0x0800; i < 0x1000; i += 4)
291 writel(0, SUNXI_DE_BE0_BASE + i);
293 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
296 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
297 unsigned int address)
299 struct sunxi_de_be_reg * const de_be =
300 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
302 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
304 writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
305 &de_be->layer0_size);
306 writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
307 writel(address << 3, &de_be->layer0_addr_low32b);
308 writel(address >> 29, &de_be->layer0_addr_high4b);
309 writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
311 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
315 * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
317 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
319 struct sunxi_ccm_reg * const ccm =
320 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
321 int value, n, m, diff;
322 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
326 * Find the lowest divider resulting in a matching clock, if there
327 * is no match, pick the closest lower clock, as monitors tend to
328 * not sync to higher frequencies.
330 for (m = 15; m > 0; m--) {
331 n = (m * dotclock) / 3000;
333 if ((n >= 9) && (n <= 127)) {
334 value = (3000 * n) / m;
335 diff = dotclock - value;
336 if (diff < best_diff) {
344 /* These are just duplicates */
348 n = (m * dotclock) / 6000;
349 if ((n >= 9) && (n <= 127)) {
350 value = (6000 * n) / m;
351 diff = dotclock - value;
352 if (diff < best_diff) {
361 debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
362 dotclock, (best_double + 1) * 3000 * best_n / best_m,
363 best_double + 1, best_n, best_m);
365 clock_set_pll3(best_n * 3000000);
367 writel(CCM_LCD_CH1_CTRL_GATE |
368 (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
369 CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
372 *clk_double = best_double;
375 static void sunxi_lcdc_init(void)
377 struct sunxi_ccm_reg * const ccm =
378 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
379 struct sunxi_lcdc_reg * const lcdc =
380 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
383 #ifdef CONFIG_MACH_SUN6I
384 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
386 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
390 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
393 writel(0, &lcdc->ctrl); /* Disable tcon */
394 writel(0, &lcdc->int0); /* Disable all interrupts */
396 /* Disable tcon0 dot clock */
397 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
399 /* Set all io lines to tristate */
400 writel(0xffffffff, &lcdc->tcon0_io_tristate);
401 writel(0xffffffff, &lcdc->tcon1_io_tristate);
404 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
405 int *clk_div, int *clk_double)
407 struct sunxi_lcdc_reg * const lcdc =
408 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
412 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
413 SUNXI_LCDC_CTRL_IO_MAP_TCON1);
415 /* Enabled, 0x1e start delay */
416 writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
417 SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
419 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
420 &lcdc->tcon1_timing_source);
421 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
422 &lcdc->tcon1_timing_scale);
423 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
424 &lcdc->tcon1_timing_out);
426 bp = mode->hsync_len + mode->left_margin;
427 total = mode->xres + mode->right_margin + bp;
428 writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
429 SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
431 bp = mode->vsync_len + mode->upper_margin;
432 total = mode->yres + mode->lower_margin + bp;
433 writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
434 SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
436 writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
437 &lcdc->tcon1_timing_sync);
439 sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
442 #ifdef CONFIG_MACH_SUN6I
443 static void sunxi_drc_init(void)
445 struct sunxi_ccm_reg * const ccm =
446 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
448 /* On sun6i the drc must be clocked even when in pass-through mode */
449 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
450 clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
454 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
456 struct sunxi_hdmi_reg * const hdmi =
457 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
459 u8 avi_info_frame[17] = {
460 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
464 u8 vendor_info_frame[19] = {
465 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
471 if (mode->pixclock_khz <= 27000)
472 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
474 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
476 if (mode->xres * 100 / mode->yres < 156)
477 avi_info_frame[5] |= 0x18; /* 4 : 3 */
479 avi_info_frame[5] |= 0x28; /* 16 : 9 */
481 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
482 checksum += avi_info_frame[i];
484 avi_info_frame[3] = 0x100 - checksum;
486 for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
487 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
489 writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
490 writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
492 for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
493 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
495 writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
496 writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
498 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
501 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
502 int clk_div, int clk_double)
504 struct sunxi_hdmi_reg * const hdmi =
505 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
508 /* Write clear interrupt status bits */
509 writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
511 if (sunxi_display.monitor == sunxi_monitor_hdmi)
512 sunxi_hdmi_setup_info_frames(mode);
514 /* Set input sync enable */
515 writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
517 /* Init various registers, select pll3 as clock source */
518 writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
519 writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
520 writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
521 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
522 writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
524 /* Setup clk div and doubler */
525 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
526 SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
528 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
530 /* Setup timing registers */
531 writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
534 x = mode->hsync_len + mode->left_margin;
535 y = mode->vsync_len + mode->upper_margin;
536 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
538 x = mode->right_margin;
539 y = mode->lower_margin;
540 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
544 writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
546 if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
547 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
549 if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
550 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
553 static void sunxi_engines_init(void)
555 sunxi_composer_init();
557 #ifdef CONFIG_MACH_SUN6I
562 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
563 unsigned int address)
565 struct sunxi_de_be_reg * const de_be =
566 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
567 struct sunxi_lcdc_reg * const lcdc =
568 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
569 struct sunxi_hdmi_reg * const hdmi =
570 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
571 int clk_div, clk_double;
573 sunxi_composer_mode_set(mode, address);
574 sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
575 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
577 setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
578 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
579 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
583 setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
586 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
589 case sunxi_monitor_none: return "none";
590 case sunxi_monitor_dvi: return "dvi";
591 case sunxi_monitor_hdmi: return "hdmi";
592 case sunxi_monitor_lcd: return "lcd";
593 case sunxi_monitor_vga: return "vga";
595 return NULL; /* never reached */
598 void *video_hw_init(void)
600 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
601 const struct ctfb_res_modes *mode;
602 struct ctfb_res_modes edid_mode;
605 int i, ret, hpd, edid;
608 memset(&sunxi_display, 0, sizeof(struct sunxi_display));
610 printf("Reserved %dkB of RAM for Framebuffer.\n",
611 CONFIG_SUNXI_FB_SIZE >> 10);
612 gd->fb_base = gd->ram_top;
614 video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
615 hpd = video_get_option_int(options, "hpd", 1);
616 edid = video_get_option_int(options, "edid", 1);
617 sunxi_display.monitor = sunxi_monitor_dvi;
618 video_get_option_string(options, "monitor", mon, sizeof(mon),
619 sunxi_get_mon_desc(sunxi_display.monitor));
620 for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
621 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
622 sunxi_display.monitor = i;
626 if (i > SUNXI_MONITOR_LAST)
627 printf("Unknown monitor: '%s', falling back to '%s'\n",
628 mon, sunxi_get_mon_desc(sunxi_display.monitor));
630 /* Always call hdp_detect, as it also enables various clocks, etc. */
631 ret = sunxi_hdmi_hpd_detect();
633 sunxi_hdmi_shutdown();
637 printf("HDMI connected: ");
639 /* Check edid if requested and we've a cable plugged in */
641 if (sunxi_hdmi_edid_get_mode(&edid_mode) == 0)
645 if (mode->vmode != FB_VMODE_NONINTERLACED) {
646 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
647 mode = &res_mode_init[RES_MODE_1024x768];
649 printf("Setting up a %dx%d %s console\n", mode->xres,
650 mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
653 sunxi_display.enabled = true;
654 sunxi_engines_init();
655 sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
658 * These are the only members of this structure that are used. All the
659 * others are driver specific. There is nothing to decribe pitch or
660 * stride, but we are lucky with our hw.
662 graphic_device->frameAdrs = gd->fb_base;
663 graphic_device->gdfIndex = GDF_32BIT_X888RGB;
664 graphic_device->gdfBytesPP = 4;
665 graphic_device->winSizeX = mode->xres;
666 graphic_device->winSizeY = mode->yres;
668 return graphic_device;
674 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
675 int sunxi_simplefb_setup(void *blob)
677 static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
680 if (!sunxi_display.enabled)
683 /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
684 offset = fdt_node_offset_by_compatible(blob, -1,
685 "allwinner,simple-framebuffer");
686 while (offset >= 0) {
687 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
691 offset = fdt_node_offset_by_compatible(blob, offset,
692 "allwinner,simple-framebuffer");
695 eprintf("Cannot setup simplefb: node not found\n");
696 return 0; /* Keep older kernels working */
699 ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
700 graphic_device->winSizeX, graphic_device->winSizeY,
701 graphic_device->winSizeX * graphic_device->gdfBytesPP,
704 eprintf("Cannot setup simplefb: Error setting properties\n");
708 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */