drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/global_data.h>
  15 #include <asm/io.h>
  16 #include <errno.h>
  17 #include <fdtdec.h>
  18 #include <fdt_support.h>
  19 #include <video_fb.h>
  20 #include "videomodes.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 struct sunxi_display {
  25         GraphicDevice graphic_device;
  26         bool enabled;
  27 } sunxi_display;
  28
  29 /*
  30  * Wait up to 200ms for value to be set in given part of reg.
  31  */
  32 static int await_completion(u32 *reg, u32 mask, u32 val)
  33 {
  34         unsigned long tmo = timer_get_us() + 200000;
  35
  36         while ((readl(reg) & mask) != val) {
  37                 if (timer_get_us() > tmo) {
  38                         printf("DDC: timeout reading EDID\n");
  39                         return -ETIME;
  40                 }
  41         }
  42         return 0;
  43 }
  44
  45 static int sunxi_hdmi_hpd_detect(void)
  46 {
  47         struct sunxi_ccm_reg * const ccm =
  48                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  49         struct sunxi_hdmi_reg * const hdmi =
  50                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  51         unsigned long tmo = timer_get_us() + 300000;
  52
  53         /* Set pll3 to 300MHz */
  54         clock_set_pll3(300000000);
  55
  56         /* Set hdmi parent to pll3 */
  57         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  58                         CCM_HDMI_CTRL_PLL3);
  59
  60         /* Set ahb gating to pass */
  61 #ifdef CONFIG_MACH_SUN6I
  62         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  63 #endif
  64         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  65
  66         /* Clock on */
  67         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  68
  69         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  70         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  71
  72         while (timer_get_us() < tmo) {
  73                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  74                         return 1;
  75         }
  76
  77         return 0;
  78 }
  79
  80 static void sunxi_hdmi_shutdown(void)
  81 {
  82         struct sunxi_ccm_reg * const ccm =
  83                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  84         struct sunxi_hdmi_reg * const hdmi =
  85                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  86
  87         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
  88         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  89         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  90 #ifdef CONFIG_MACH_SUN6I
  91         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  92 #endif
  93         clock_set_pll3(0);
  94 }
  95
  96 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
  97 {
  98         struct sunxi_hdmi_reg * const hdmi =
  99                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 100
 101         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 102         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 103                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 104                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 105                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 106 #ifndef CONFIG_MACH_SUN6I
 107         writel(n, &hdmi->ddc_byte_count);
 108         writel(cmnd, &hdmi->ddc_cmnd);
 109 #else
 110         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 111 #endif
 112         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 113
 114         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 115 }
 116
 117 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 118 {
 119         struct sunxi_hdmi_reg * const hdmi =
 120                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 121         int i, n;
 122
 123         while (count > 0) {
 124                 if (count > 16)
 125                         n = 16;
 126                 else
 127                         n = count;
 128
 129                 if (sunxi_hdmi_ddc_do_command(
 130                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 131                                 offset, n))
 132                         return -ETIME;
 133
 134                 for (i = 0; i < n; i++)
 135                         *buf++ = readb(&hdmi->ddc_fifo_data);
 136
 137                 offset += n;
 138                 count -= n;
 139         }
 140
 141         return 0;
 142 }
 143
 144 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 145 {
 146         int r, retries = 2;
 147
 148         do {
 149                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 150                 if (r)
 151                         continue;
 152                 r = edid_check_checksum(buf);
 153                 if (r) {
 154                         printf("EDID block %d: checksum error%s\n",
 155                                block, retries ? ", retrying" : "");
 156                 }
 157         } while (r && retries--);
 158
 159         return r;
 160 }
 161
 162 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode, char *monitor)
 163 {
 164         struct edid1_info edid1;
 165         struct edid_cea861_info cea681[4];
 166         struct edid_detailed_timing *t =
 167                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 168         struct sunxi_hdmi_reg * const hdmi =
 169                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 170         struct sunxi_ccm_reg * const ccm =
 171                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 172         int i, r, ext_blocks = 0;
 173
 174         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 175         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 176                &hdmi->pad_ctrl1);
 177         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 178                &hdmi->pll_ctrl);
 179         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 180
 181         /* Reset i2c controller */
 182         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 183         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 184                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 185                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 186                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 187         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 188                 return -EIO;
 189
 190         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 191 #ifndef CONFIG_MACH_SUN6I
 192         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 193                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 194 #endif
 195
 196         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 197         if (r == 0) {
 198                 r = edid_check_info(&edid1);
 199                 if (r) {
 200                         printf("EDID: invalid EDID data\n");
 201                         r = -EINVAL;
 202                 }
 203         }
 204         if (r == 0) {
 205                 ext_blocks = edid1.extension_flag;
 206                 if (ext_blocks > 4)
 207                         ext_blocks = 4;
 208                 for (i = 0; i < ext_blocks; i++) {
 209                         if (sunxi_hdmi_edid_get_block(1 + i,
 210                                                 (u8 *)&cea681[i]) != 0) {
 211                                 ext_blocks = i;
 212                                 break;
 213                         }
 214                 }
 215         }
 216
 217         /* Disable DDC engine, no longer needed */
 218         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 219         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 220
 221         if (r)
 222                 return r;
 223
 224         /* We want version 1.3 or 1.2 with detailed timing info */
 225         if (edid1.version != 1 || (edid1.revision < 3 &&
 226                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 227                 printf("EDID: unsupported version %d.%d\n",
 228                        edid1.version, edid1.revision);
 229                 return -EINVAL;
 230         }
 231
 232         /* Take the first usable detailed timing */
 233         for (i = 0; i < 4; i++, t++) {
 234                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 235                 if (r == 0)
 236                         break;
 237         }
 238         if (i == 4) {
 239                 printf("EDID: no usable detailed timing found\n");
 240                 return -ENOENT;
 241         }
 242
 243         /* Check for basic audio support, if found enable hdmi output */
 244         strcpy(monitor, "dvi");
 245         for (i = 0; i < ext_blocks; i++) {
 246                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 247                     cea681[i].revision < 2)
 248                         continue;
 249
 250                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 251                         strcpy(monitor, "hdmi");
 252         }
 253
 254         return 0;
 255 }
 256
 257 /*
 258  * This is the entity that mixes and matches the different layers and inputs.
 259  * Allwinner calls it the back-end, but i like composer better.
 260  */
 261 static void sunxi_composer_init(void)
 262 {
 263         struct sunxi_ccm_reg * const ccm =
 264                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 265         struct sunxi_de_be_reg * const de_be =
 266                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 267         int i;
 268
 269 #ifdef CONFIG_MACH_SUN6I
 270         /* Reset off */
 271         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 272 #endif
 273
 274         /* Clocks on */
 275         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 276         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 277         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 278
 279         /* Engine bug, clear registers after reset */
 280         for (i = 0x0800; i < 0x1000; i += 4)
 281                 writel(0, SUNXI_DE_BE0_BASE + i);
 282
 283         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 284 }
 285
 286 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 287                                     unsigned int address)
 288 {
 289         struct sunxi_de_be_reg * const de_be =
 290                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 291
 292         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 293                &de_be->disp_size);
 294         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 295                &de_be->layer0_size);
 296         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 297         writel(address << 3, &de_be->layer0_addr_low32b);
 298         writel(address >> 29, &de_be->layer0_addr_high4b);
 299         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 300
 301         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 302 }
 303
 304 /*
 305  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 306  */
 307 static void sunxi_lcdc_pll_set(int dotclock, int *clk_div, int *clk_double)
 308 {
 309         struct sunxi_ccm_reg * const ccm =
 310                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 311         int value, n, m, diff;
 312         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 313         int best_double = 0;
 314
 315         /*
 316          * Find the lowest divider resulting in a matching clock, if there
 317          * is no match, pick the closest lower clock, as monitors tend to
 318          * not sync to higher frequencies.
 319          */
 320         for (m = 15; m > 0; m--) {
 321                 n = (m * dotclock) / 3000;
 322
 323                 if ((n >= 9) && (n <= 127)) {
 324                         value = (3000 * n) / m;
 325                         diff = dotclock - value;
 326                         if (diff < best_diff) {
 327                                 best_diff = diff;
 328                                 best_m = m;
 329                                 best_n = n;
 330                                 best_double = 0;
 331                         }
 332                 }
 333
 334                 /* These are just duplicates */
 335                 if (!(m & 1))
 336                         continue;
 337
 338                 n = (m * dotclock) / 6000;
 339                 if ((n >= 9) && (n <= 127)) {
 340                         value = (6000 * n) / m;
 341                         diff = dotclock - value;
 342                         if (diff < best_diff) {
 343                                 best_diff = diff;
 344                                 best_m = m;
 345                                 best_n = n;
 346                                 best_double = 1;
 347                         }
 348                 }
 349         }
 350
 351         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 352               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 353               best_double + 1, best_n, best_m);
 354
 355         clock_set_pll3(best_n * 3000000);
 356
 357         writel(CCM_LCD_CH1_CTRL_GATE |
 358             (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X : CCM_LCD_CH1_CTRL_PLL3) |
 359             CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 360
 361         *clk_div = best_m;
 362         *clk_double = best_double;
 363 }
 364
 365 static void sunxi_lcdc_init(void)
 366 {
 367         struct sunxi_ccm_reg * const ccm =
 368                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 369         struct sunxi_lcdc_reg * const lcdc =
 370                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 371
 372         /* Reset off */
 373 #ifdef CONFIG_MACH_SUN6I
 374         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 375 #else
 376         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 377 #endif
 378
 379         /* Clock on */
 380         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 381
 382         /* Init lcdc */
 383         writel(0, &lcdc->ctrl); /* Disable tcon */
 384         writel(0, &lcdc->int0); /* Disable all interrupts */
 385
 386         /* Disable tcon0 dot clock */
 387         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 388
 389         /* Set all io lines to tristate */
 390         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 391         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 392 }
 393
 394 static void sunxi_lcdc_mode_set(const struct ctfb_res_modes *mode,
 395                                 int *clk_div, int *clk_double)
 396 {
 397         struct sunxi_lcdc_reg * const lcdc =
 398                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 399         int bp, total;
 400
 401         /* Use tcon1 */
 402         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 403                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 404
 405         /* Enabled, 0x1e start delay */
 406         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 407                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 408
 409         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 410                &lcdc->tcon1_timing_source);
 411         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 412                &lcdc->tcon1_timing_scale);
 413         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 414                &lcdc->tcon1_timing_out);
 415
 416         bp = mode->hsync_len + mode->left_margin;
 417         total = mode->xres + mode->right_margin + bp;
 418         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 419                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 420
 421         bp = mode->vsync_len + mode->upper_margin;
 422         total = mode->yres + mode->lower_margin + bp;
 423         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 424                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 425
 426         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 427                &lcdc->tcon1_timing_sync);
 428
 429         sunxi_lcdc_pll_set(mode->pixclock_khz, clk_div, clk_double);
 430 }
 431
 432 #ifdef CONFIG_MACH_SUN6I
 433 static void sunxi_drc_init(void)
 434 {
 435         struct sunxi_ccm_reg * const ccm =
 436                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 437
 438         /* On sun6i the drc must be clocked even when in pass-through mode */
 439         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 440         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 441 }
 442 #endif
 443
 444 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 445 {
 446         struct sunxi_hdmi_reg * const hdmi =
 447                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 448         u8 checksum = 0;
 449         u8 avi_info_frame[17] = {
 450                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 451                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 452                 0x00
 453         };
 454         u8 vendor_info_frame[19] = {
 455                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 456                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 457                 0x00, 0x00, 0x00
 458         };
 459         int i;
 460
 461         if (mode->pixclock_khz <= 27000)
 462                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 463         else
 464                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 465
 466         if (mode->xres * 100 / mode->yres < 156)
 467                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 468         else
 469                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 470
 471         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 472                 checksum += avi_info_frame[i];
 473
 474         avi_info_frame[3] = 0x100 - checksum;
 475
 476         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 477                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 478
 479         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 480         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 481
 482         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 483                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 484
 485         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 486         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 487
 488         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 489 }
 490
 491 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 492                                 bool hdmi_mode, int clk_div, int clk_double)
 493 {
 494         struct sunxi_hdmi_reg * const hdmi =
 495                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 496         int x, y;
 497
 498         /* Write clear interrupt status bits */
 499         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 500
 501         if (hdmi_mode)
 502                 sunxi_hdmi_setup_info_frames(mode);
 503
 504         /* Init various registers, select pll3 as clock source */
 505         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 506         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 507         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 508         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 509         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 510
 511         /* Setup clk div and doubler */
 512         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 513                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 514         if (!clk_double)
 515                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 516
 517         /* Setup timing registers */
 518         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 519                &hdmi->video_size);
 520
 521         x = mode->hsync_len + mode->left_margin;
 522         y = mode->vsync_len + mode->upper_margin;
 523         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 524
 525         x = mode->right_margin;
 526         y = mode->lower_margin;
 527         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 528
 529         x = mode->hsync_len;
 530         y = mode->vsync_len;
 531         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 532
 533         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 534                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 535
 536         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 537                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 538 }
 539
 540 static void sunxi_engines_init(void)
 541 {
 542         sunxi_composer_init();
 543         sunxi_lcdc_init();
 544 #ifdef CONFIG_MACH_SUN6I
 545         sunxi_drc_init();
 546 #endif
 547 }
 548
 549 static void sunxi_mode_set(const struct ctfb_res_modes *mode, char *monitor,
 550                            unsigned int address)
 551 {
 552         struct sunxi_de_be_reg * const de_be =
 553                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 554         struct sunxi_lcdc_reg * const lcdc =
 555                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 556         struct sunxi_hdmi_reg * const hdmi =
 557                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 558         int clk_div, clk_double;
 559         int retries = 3;
 560         bool hdmi_mode = strcmp(monitor, "hdmi") == 0;
 561
 562 retry:
 563         clrbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 564         clrbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 565         clrbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 566
 567         sunxi_composer_mode_set(mode, address);
 568         sunxi_lcdc_mode_set(mode, &clk_div, &clk_double);
 569         sunxi_hdmi_mode_set(mode, hdmi_mode, clk_div, clk_double);
 570
 571         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 572         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 573
 574         udelay(1000000 / mode->refresh + 500);
 575
 576         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 577
 578         udelay(1000000 / mode->refresh + 500);
 579
 580         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 581
 582         udelay(1000000 / mode->refresh + 500);
 583
 584         /*
 585          * Sometimes the display pipeline does not sync up properly, if
 586          * this happens the hdmi fifo underrun or overrun bits are set.
 587          */
 588         if (readl(&hdmi->irq) &
 589             (SUNXI_HDMI_IRQ_STATUS_FIFO_UF | SUNXI_HDMI_IRQ_STATUS_FIFO_OF)) {
 590                 if (retries--)
 591                         goto retry;
 592                 printf("HDMI fifo under or overrun\n");
 593         }
 594 }
 595
 596 void *video_hw_init(void)
 597 {
 598         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 599         const struct ctfb_res_modes *mode;
 600         struct ctfb_res_modes edid_mode;
 601         const char *options;
 602         unsigned int depth;
 603         int ret, hpd, edid;
 604         char monitor[16];
 605
 606         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 607
 608         printf("Reserved %dkB of RAM for Framebuffer.\n",
 609                CONFIG_SUNXI_FB_SIZE >> 10);
 610         gd->fb_base = gd->ram_top;
 611
 612         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, &depth, &options);
 613         hpd = video_get_option_int(options, "hpd", 1);
 614         edid = video_get_option_int(options, "edid", 1);
 615         video_get_option_string(options, "monitor", monitor, sizeof(monitor),
 616                                 "dvi");
 617
 618         /* Always call hdp_detect, as it also enables various clocks, etc. */
 619         ret = sunxi_hdmi_hpd_detect();
 620         if (hpd && !ret) {
 621                 sunxi_hdmi_shutdown();
 622                 return NULL;
 623         }
 624         if (ret)
 625                 printf("HDMI connected: ");
 626
 627         /* Check edid if requested and we've a cable plugged in */
 628         if (edid && ret) {
 629                 if (sunxi_hdmi_edid_get_mode(&edid_mode, monitor) == 0)
 630                         mode = &edid_mode;
 631         }
 632
 633         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 634                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 635                 mode = &res_mode_init[RES_MODE_1024x768];
 636         } else {
 637                 printf("Setting up a %dx%d %s console\n",
 638                        mode->xres, mode->yres, monitor);
 639         }
 640
 641         sunxi_display.enabled = true;
 642         sunxi_engines_init();
 643         sunxi_mode_set(mode, monitor, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 644
 645         /*
 646          * These are the only members of this structure that are used. All the
 647          * others are driver specific. There is nothing to decribe pitch or
 648          * stride, but we are lucky with our hw.
 649          */
 650         graphic_device->frameAdrs = gd->fb_base;
 651         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 652         graphic_device->gdfBytesPP = 4;
 653         graphic_device->winSizeX = mode->xres;
 654         graphic_device->winSizeY = mode->yres;
 655
 656         return graphic_device;
 657 }
 658
 659 /*
 660  * Simplefb support.
 661  */
 662 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 663 int sunxi_simplefb_setup(void *blob)
 664 {
 665         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 666         int offset, ret;
 667
 668         if (!sunxi_display.enabled)
 669                 return 0;
 670
 671         /* Find a framebuffer node, with pipeline == "de_be0-lcd0-hdmi" */
 672         offset = fdt_node_offset_by_compatible(blob, -1,
 673                                                "allwinner,simple-framebuffer");
 674         while (offset >= 0) {
 675                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 676                                       "de_be0-lcd0-hdmi");
 677                 if (ret == 0)
 678                         break;
 679                 offset = fdt_node_offset_by_compatible(blob, offset,
 680                                                "allwinner,simple-framebuffer");
 681         }
 682         if (offset < 0) {
 683                 eprintf("Cannot setup simplefb: node not found\n");
 684                 return 0; /* Keep older kernels working */
 685         }
 686
 687         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 688                         graphic_device->winSizeX, graphic_device->winSizeY,
 689                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 690                         "x8r8g8b8");
 691         if (ret)
 692                 eprintf("Cannot setup simplefb: Error setting properties\n");
 693
 694         return ret;
 695 }
 696 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */