drivers/video/sunxi_display.c

   1 /*
   2  * Display driver for Allwinner SoCs.
   3  *
   4  * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/display.h>
  14 #include <asm/arch/gpio.h>
  15 #include <asm/global_data.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <errno.h>
  19 #include <fdtdec.h>
  20 #include <fdt_support.h>
  21 #include <video_fb.h>
  22 #include "videomodes.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 enum sunxi_monitor {
  27         sunxi_monitor_none,
  28         sunxi_monitor_dvi,
  29         sunxi_monitor_hdmi,
  30         sunxi_monitor_lcd,
  31         sunxi_monitor_vga,
  32 };
  33 #define SUNXI_MONITOR_LAST sunxi_monitor_vga
  34
  35 struct sunxi_display {
  36         GraphicDevice graphic_device;
  37         bool enabled;
  38         enum sunxi_monitor monitor;
  39         unsigned int depth;
  40 } sunxi_display;
  41
  42 /*
  43  * Wait up to 200ms for value to be set in given part of reg.
  44  */
  45 static int await_completion(u32 *reg, u32 mask, u32 val)
  46 {
  47         unsigned long tmo = timer_get_us() + 200000;
  48
  49         while ((readl(reg) & mask) != val) {
  50                 if (timer_get_us() > tmo) {
  51                         printf("DDC: timeout reading EDID\n");
  52                         return -ETIME;
  53                 }
  54         }
  55         return 0;
  56 }
  57
  58 static int sunxi_hdmi_hpd_detect(void)
  59 {
  60         struct sunxi_ccm_reg * const ccm =
  61                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  62         struct sunxi_hdmi_reg * const hdmi =
  63                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  64         unsigned long tmo = timer_get_us() + 300000;
  65
  66         /* Set pll3 to 300MHz */
  67         clock_set_pll3(300000000);
  68
  69         /* Set hdmi parent to pll3 */
  70         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
  71                         CCM_HDMI_CTRL_PLL3);
  72
  73         /* Set ahb gating to pass */
  74 #ifdef CONFIG_MACH_SUN6I
  75         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
  76 #endif
  77         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
  78
  79         /* Clock on */
  80         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
  81
  82         writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
  83         writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
  84
  85         while (timer_get_us() < tmo) {
  86                 if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
  87                         return 1;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static void sunxi_hdmi_shutdown(void)
  94 {
  95         struct sunxi_ccm_reg * const ccm =
  96                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  97         struct sunxi_hdmi_reg * const hdmi =
  98                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
  99
 100         clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
 101         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 102         clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 103 #ifdef CONFIG_MACH_SUN6I
 104         clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 105 #endif
 106         clock_set_pll3(0);
 107 }
 108
 109 static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
 110 {
 111         struct sunxi_hdmi_reg * const hdmi =
 112                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 113
 114         setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
 115         writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
 116                SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
 117                SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
 118                SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
 119 #ifndef CONFIG_MACH_SUN6I
 120         writel(n, &hdmi->ddc_byte_count);
 121         writel(cmnd, &hdmi->ddc_cmnd);
 122 #else
 123         writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
 124 #endif
 125         setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
 126
 127         return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
 128 }
 129
 130 static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
 131 {
 132         struct sunxi_hdmi_reg * const hdmi =
 133                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 134         int i, n;
 135
 136         while (count > 0) {
 137                 if (count > 16)
 138                         n = 16;
 139                 else
 140                         n = count;
 141
 142                 if (sunxi_hdmi_ddc_do_command(
 143                                 SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
 144                                 offset, n))
 145                         return -ETIME;
 146
 147                 for (i = 0; i < n; i++)
 148                         *buf++ = readb(&hdmi->ddc_fifo_data);
 149
 150                 offset += n;
 151                 count -= n;
 152         }
 153
 154         return 0;
 155 }
 156
 157 static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
 158 {
 159         int r, retries = 2;
 160
 161         do {
 162                 r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
 163                 if (r)
 164                         continue;
 165                 r = edid_check_checksum(buf);
 166                 if (r) {
 167                         printf("EDID block %d: checksum error%s\n",
 168                                block, retries ? ", retrying" : "");
 169                 }
 170         } while (r && retries--);
 171
 172         return r;
 173 }
 174
 175 static int sunxi_hdmi_edid_get_mode(struct ctfb_res_modes *mode)
 176 {
 177         struct edid1_info edid1;
 178         struct edid_cea861_info cea681[4];
 179         struct edid_detailed_timing *t =
 180                 (struct edid_detailed_timing *)edid1.monitor_details.timing;
 181         struct sunxi_hdmi_reg * const hdmi =
 182                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 183         struct sunxi_ccm_reg * const ccm =
 184                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 185         int i, r, ext_blocks = 0;
 186
 187         /* SUNXI_HDMI_CTRL_ENABLE & PAD_CTRL0 are already set by hpd_detect */
 188         writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
 189                &hdmi->pad_ctrl1);
 190         writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
 191                &hdmi->pll_ctrl);
 192         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 193
 194         /* Reset i2c controller */
 195         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 196         writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
 197                SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
 198                SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
 199                SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
 200         if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
 201                 return -EIO;
 202
 203         writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
 204 #ifndef CONFIG_MACH_SUN6I
 205         writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
 206                SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
 207 #endif
 208
 209         r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
 210         if (r == 0) {
 211                 r = edid_check_info(&edid1);
 212                 if (r) {
 213                         printf("EDID: invalid EDID data\n");
 214                         r = -EINVAL;
 215                 }
 216         }
 217         if (r == 0) {
 218                 ext_blocks = edid1.extension_flag;
 219                 if (ext_blocks > 4)
 220                         ext_blocks = 4;
 221                 for (i = 0; i < ext_blocks; i++) {
 222                         if (sunxi_hdmi_edid_get_block(1 + i,
 223                                                 (u8 *)&cea681[i]) != 0) {
 224                                 ext_blocks = i;
 225                                 break;
 226                         }
 227                 }
 228         }
 229
 230         /* Disable DDC engine, no longer needed */
 231         clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
 232         clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
 233
 234         if (r)
 235                 return r;
 236
 237         /* We want version 1.3 or 1.2 with detailed timing info */
 238         if (edid1.version != 1 || (edid1.revision < 3 &&
 239                         !EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
 240                 printf("EDID: unsupported version %d.%d\n",
 241                        edid1.version, edid1.revision);
 242                 return -EINVAL;
 243         }
 244
 245         /* Take the first usable detailed timing */
 246         for (i = 0; i < 4; i++, t++) {
 247                 r = video_edid_dtd_to_ctfb_res_modes(t, mode);
 248                 if (r == 0)
 249                         break;
 250         }
 251         if (i == 4) {
 252                 printf("EDID: no usable detailed timing found\n");
 253                 return -ENOENT;
 254         }
 255
 256         /* Check for basic audio support, if found enable hdmi output */
 257         sunxi_display.monitor = sunxi_monitor_dvi;
 258         for (i = 0; i < ext_blocks; i++) {
 259                 if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
 260                     cea681[i].revision < 2)
 261                         continue;
 262
 263                 if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
 264                         sunxi_display.monitor = sunxi_monitor_hdmi;
 265         }
 266
 267         return 0;
 268 }
 269
 270 /*
 271  * This is the entity that mixes and matches the different layers and inputs.
 272  * Allwinner calls it the back-end, but i like composer better.
 273  */
 274 static void sunxi_composer_init(void)
 275 {
 276         struct sunxi_ccm_reg * const ccm =
 277                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 278         struct sunxi_de_be_reg * const de_be =
 279                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 280         int i;
 281
 282 #ifdef CONFIG_MACH_SUN6I
 283         /* Reset off */
 284         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
 285 #endif
 286
 287         /* Clocks on */
 288         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
 289         setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
 290         clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
 291
 292         /* Engine bug, clear registers after reset */
 293         for (i = 0x0800; i < 0x1000; i += 4)
 294                 writel(0, SUNXI_DE_BE0_BASE + i);
 295
 296         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 297 }
 298
 299 static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
 300                                     unsigned int address)
 301 {
 302         struct sunxi_de_be_reg * const de_be =
 303                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 304
 305         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 306                &de_be->disp_size);
 307         writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
 308                &de_be->layer0_size);
 309         writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
 310         writel(address << 3, &de_be->layer0_addr_low32b);
 311         writel(address >> 29, &de_be->layer0_addr_high4b);
 312         writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
 313
 314         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
 315 }
 316
 317 static void sunxi_composer_enable(void)
 318 {
 319         struct sunxi_de_be_reg * const de_be =
 320                 (struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
 321
 322         setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
 323         setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
 324 }
 325
 326 /*
 327  * LCDC, what allwinner calls a CRTC, so timing controller and serializer.
 328  */
 329 static void sunxi_lcdc_pll_set(int tcon, int dotclock,
 330                                int *clk_div, int *clk_double)
 331 {
 332         struct sunxi_ccm_reg * const ccm =
 333                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 334         int value, n, m, min_m, max_m, diff;
 335         int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
 336         int best_double = 0;
 337
 338         if (tcon == 0) {
 339                 min_m = 6;
 340                 max_m = 127;
 341         } else {
 342                 min_m = 1;
 343                 max_m = 15;
 344         }
 345
 346         /*
 347          * Find the lowest divider resulting in a matching clock, if there
 348          * is no match, pick the closest lower clock, as monitors tend to
 349          * not sync to higher frequencies.
 350          */
 351         for (m = min_m; m <= max_m; m++) {
 352                 n = (m * dotclock) / 3000;
 353
 354                 if ((n >= 9) && (n <= 127)) {
 355                         value = (3000 * n) / m;
 356                         diff = dotclock - value;
 357                         if (diff < best_diff) {
 358                                 best_diff = diff;
 359                                 best_m = m;
 360                                 best_n = n;
 361                                 best_double = 0;
 362                         }
 363                 }
 364
 365                 /* These are just duplicates */
 366                 if (!(m & 1))
 367                         continue;
 368
 369                 n = (m * dotclock) / 6000;
 370                 if ((n >= 9) && (n <= 127)) {
 371                         value = (6000 * n) / m;
 372                         diff = dotclock - value;
 373                         if (diff < best_diff) {
 374                                 best_diff = diff;
 375                                 best_m = m;
 376                                 best_n = n;
 377                                 best_double = 1;
 378                         }
 379                 }
 380         }
 381
 382         debug("dotclock: %dkHz = %dkHz: (%d * 3MHz * %d) / %d\n",
 383               dotclock, (best_double + 1) * 3000 * best_n / best_m,
 384               best_double + 1, best_n, best_m);
 385
 386         clock_set_pll3(best_n * 3000000);
 387
 388         if (tcon == 0) {
 389                 writel(CCM_LCD_CH0_CTRL_GATE | CCM_LCD_CH0_CTRL_RST |
 390                        (best_double ? CCM_LCD_CH0_CTRL_PLL3_2X :
 391                                       CCM_LCD_CH0_CTRL_PLL3),
 392                        &ccm->lcd0_ch0_clk_cfg);
 393         } else {
 394                 writel(CCM_LCD_CH1_CTRL_GATE |
 395                        (best_double ? CCM_LCD_CH1_CTRL_PLL3_2X :
 396                                       CCM_LCD_CH1_CTRL_PLL3) |
 397                        CCM_LCD_CH1_CTRL_M(best_m), &ccm->lcd0_ch1_clk_cfg);
 398         }
 399
 400         *clk_div = best_m;
 401         *clk_double = best_double;
 402 }
 403
 404 static void sunxi_lcdc_init(void)
 405 {
 406         struct sunxi_ccm_reg * const ccm =
 407                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 408         struct sunxi_lcdc_reg * const lcdc =
 409                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 410
 411         /* Reset off */
 412 #ifdef CONFIG_MACH_SUN6I
 413         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 414 #else
 415         setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
 416 #endif
 417
 418         /* Clock on */
 419         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 420
 421         /* Init lcdc */
 422         writel(0, &lcdc->ctrl); /* Disable tcon */
 423         writel(0, &lcdc->int0); /* Disable all interrupts */
 424
 425         /* Disable tcon0 dot clock */
 426         clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE);
 427
 428         /* Set all io lines to tristate */
 429         writel(0xffffffff, &lcdc->tcon0_io_tristate);
 430         writel(0xffffffff, &lcdc->tcon1_io_tristate);
 431 }
 432
 433 static void sunxi_lcdc_enable(void)
 434 {
 435         struct sunxi_lcdc_reg * const lcdc =
 436                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 437
 438         setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE);
 439 }
 440
 441 static void sunxi_lcdc_panel_enable(void)
 442 {
 443         int pin;
 444
 445         /*
 446          * Start with backlight disabled to avoid the screen flashing to
 447          * white while the lcd inits.
 448          */
 449         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 450         if (pin != -1) {
 451                 gpio_request(pin, "lcd_backlight_enable");
 452                 gpio_direction_output(pin, 0);
 453         }
 454
 455         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 456         if (pin != -1) {
 457                 gpio_request(pin, "lcd_backlight_pwm");
 458                 /* backlight pwm is inverted, set to 1 to disable backlight */
 459                 gpio_direction_output(pin, 1);
 460         }
 461
 462         /* Give the backlight some time to turn off and power up the panel. */
 463         mdelay(40);
 464         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
 465         if (pin != -1) {
 466                 gpio_request(pin, "lcd_power");
 467                 gpio_direction_output(pin, 1);
 468         }
 469 }
 470
 471 static void sunxi_lcdc_backlight_enable(void)
 472 {
 473         int pin;
 474
 475         /*
 476          * We want to have scanned out at least one frame before enabling the
 477          * backlight to avoid the screen flashing to white when we enable it.
 478          */
 479         mdelay(40);
 480
 481         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
 482         if (pin != -1)
 483                 gpio_direction_output(pin, 1);
 484
 485         pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
 486         if (pin != -1) {
 487                 /* backlight pwm is inverted, set to 0 to enable backlight */
 488                 gpio_direction_output(pin, 0);
 489         }
 490 }
 491
 492 static int sunxi_lcdc_get_clk_delay(const struct ctfb_res_modes *mode)
 493 {
 494         int delay;
 495
 496         delay = mode->lower_margin + mode->vsync_len + mode->upper_margin - 2;
 497         return (delay > 30) ? 30 : delay;
 498 }
 499
 500 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
 501 {
 502         struct sunxi_lcdc_reg * const lcdc =
 503                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 504         int bp, clk_delay, clk_div, clk_double, pin, total, val;
 505
 506         for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++)
 507                 sunxi_gpio_set_cfgpin(pin, SUNXI_GPD0_LCD0);
 508
 509         sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 510
 511         /* Use tcon0 */
 512         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 513                         SUNXI_LCDC_CTRL_IO_MAP_TCON0);
 514
 515         clk_delay = sunxi_lcdc_get_clk_delay(mode);
 516         writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |
 517                SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl);
 518
 519         writel(SUNXI_LCDC_TCON0_DCLK_ENABLE |
 520                SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk);
 521
 522         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 523                &lcdc->tcon0_timing_active);
 524
 525         bp = mode->hsync_len + mode->left_margin;
 526         total = mode->xres + mode->right_margin + bp;
 527         writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) |
 528                SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h);
 529
 530         bp = mode->vsync_len + mode->upper_margin;
 531         total = mode->yres + mode->lower_margin + bp;
 532         writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) |
 533                SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v);
 534
 535         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 536                &lcdc->tcon0_timing_sync);
 537
 538         /* We only support hv-sync parallel lcd-s for now */
 539         writel(0, &lcdc->tcon0_hv_intf);
 540         writel(0, &lcdc->tcon0_cpu_intf);
 541
 542         if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
 543                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]);
 544                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]);
 545                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]);
 546                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]);
 547                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]);
 548                 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]);
 549                 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]);
 550                 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]);
 551                 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]);
 552                 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]);
 553                 writel(((sunxi_display.depth == 18) ?
 554                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 :
 555                         SUNXI_LCDC_TCON0_FRM_CTRL_RGB565),
 556                        &lcdc->tcon0_frm_ctrl);
 557         }
 558
 559         val = 0;
 560         if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
 561                 val |= SUNXI_LCDC_TCON_HSYNC_MASK;
 562         if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
 563                 val |= SUNXI_LCDC_TCON_VSYNC_MASK;
 564         writel(val, &lcdc->tcon0_io_polarity);
 565
 566         writel(0, &lcdc->tcon0_io_tristate);
 567 }
 568
 569 static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 570                                       int *clk_div, int *clk_double)
 571 {
 572         struct sunxi_lcdc_reg * const lcdc =
 573                 (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 574         int bp, total;
 575
 576         /* Use tcon1 */
 577         clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 578                         SUNXI_LCDC_CTRL_IO_MAP_TCON1);
 579
 580         /* Enabled, 0x1e start delay */
 581         writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |
 582                SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(0x1e), &lcdc->tcon1_ctrl);
 583
 584         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 585                &lcdc->tcon1_timing_source);
 586         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 587                &lcdc->tcon1_timing_scale);
 588         writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(mode->yres),
 589                &lcdc->tcon1_timing_out);
 590
 591         bp = mode->hsync_len + mode->left_margin;
 592         total = mode->xres + mode->right_margin + bp;
 593         writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) |
 594                SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h);
 595
 596         bp = mode->vsync_len + mode->upper_margin;
 597         total = mode->yres + mode->lower_margin + bp;
 598         writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) |
 599                SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v);
 600
 601         writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len),
 602                &lcdc->tcon1_timing_sync);
 603
 604         sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double);
 605 }
 606
 607 static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
 608 {
 609         struct sunxi_hdmi_reg * const hdmi =
 610                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 611         u8 checksum = 0;
 612         u8 avi_info_frame[17] = {
 613                 0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
 614                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 615                 0x00
 616         };
 617         u8 vendor_info_frame[19] = {
 618                 0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
 619                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 620                 0x00, 0x00, 0x00
 621         };
 622         int i;
 623
 624         if (mode->pixclock_khz <= 27000)
 625                 avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
 626         else
 627                 avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
 628
 629         if (mode->xres * 100 / mode->yres < 156)
 630                 avi_info_frame[5] |= 0x18; /* 4 : 3 */
 631         else
 632                 avi_info_frame[5] |= 0x28; /* 16 : 9 */
 633
 634         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 635                 checksum += avi_info_frame[i];
 636
 637         avi_info_frame[3] = 0x100 - checksum;
 638
 639         for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
 640                 writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
 641
 642         writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
 643         writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
 644
 645         for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
 646                 writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
 647
 648         writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
 649         writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
 650
 651         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
 652 }
 653
 654 static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
 655                                 int clk_div, int clk_double)
 656 {
 657         struct sunxi_hdmi_reg * const hdmi =
 658                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 659         int x, y;
 660
 661         /* Write clear interrupt status bits */
 662         writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
 663
 664         if (sunxi_display.monitor == sunxi_monitor_hdmi)
 665                 sunxi_hdmi_setup_info_frames(mode);
 666
 667         /* Set input sync enable */
 668         writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
 669
 670         /* Init various registers, select pll3 as clock source */
 671         writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
 672         writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
 673         writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
 674         writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
 675         writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
 676
 677         /* Setup clk div and doubler */
 678         clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
 679                         SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
 680         if (!clk_double)
 681                 setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
 682
 683         /* Setup timing registers */
 684         writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
 685                &hdmi->video_size);
 686
 687         x = mode->hsync_len + mode->left_margin;
 688         y = mode->vsync_len + mode->upper_margin;
 689         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
 690
 691         x = mode->right_margin;
 692         y = mode->lower_margin;
 693         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
 694
 695         x = mode->hsync_len;
 696         y = mode->vsync_len;
 697         writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
 698
 699         if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
 700                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
 701
 702         if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
 703                 setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
 704 }
 705
 706 static void sunxi_hdmi_enable(void)
 707 {
 708         struct sunxi_hdmi_reg * const hdmi =
 709                 (struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
 710
 711         udelay(100);
 712         setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
 713 }
 714
 715 static void sunxi_drc_init(void)
 716 {
 717 #ifdef CONFIG_MACH_SUN6I
 718         struct sunxi_ccm_reg * const ccm =
 719                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 720
 721         /* On sun6i the drc must be clocked even when in pass-through mode */
 722         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
 723         clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
 724 #endif
 725 }
 726
 727 static void sunxi_engines_init(void)
 728 {
 729         sunxi_composer_init();
 730         sunxi_lcdc_init();
 731         sunxi_drc_init();
 732 }
 733
 734 static void sunxi_mode_set(const struct ctfb_res_modes *mode,
 735                            unsigned int address)
 736 {
 737         switch (sunxi_display.monitor) {
 738         case sunxi_monitor_none:
 739                 break;
 740         case sunxi_monitor_dvi:
 741         case sunxi_monitor_hdmi: {
 742                 int clk_div, clk_double;
 743                 sunxi_composer_mode_set(mode, address);
 744                 sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double);
 745                 sunxi_hdmi_mode_set(mode, clk_div, clk_double);
 746                 sunxi_composer_enable();
 747                 sunxi_lcdc_enable();
 748                 sunxi_hdmi_enable();
 749                 }
 750                 break;
 751         case sunxi_monitor_lcd:
 752                 sunxi_lcdc_panel_enable();
 753                 sunxi_composer_mode_set(mode, address);
 754                 sunxi_lcdc_tcon0_mode_set(mode);
 755                 sunxi_composer_enable();
 756                 sunxi_lcdc_enable();
 757                 sunxi_lcdc_backlight_enable();
 758                 break;
 759         case sunxi_monitor_vga:
 760                 break;
 761         }
 762 }
 763
 764 static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
 765 {
 766         switch (monitor) {
 767         case sunxi_monitor_none:        return "none";
 768         case sunxi_monitor_dvi:         return "dvi";
 769         case sunxi_monitor_hdmi:        return "hdmi";
 770         case sunxi_monitor_lcd:         return "lcd";
 771         case sunxi_monitor_vga:         return "vga";
 772         }
 773         return NULL; /* never reached */
 774 }
 775
 776 void *video_hw_init(void)
 777 {
 778         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 779         const struct ctfb_res_modes *mode;
 780         struct ctfb_res_modes custom;
 781         const char *options;
 782         int i, ret, hpd, edid;
 783         char mon[16];
 784         char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
 785
 786         memset(&sunxi_display, 0, sizeof(struct sunxi_display));
 787
 788         printf("Reserved %dkB of RAM for Framebuffer.\n",
 789                CONFIG_SUNXI_FB_SIZE >> 10);
 790         gd->fb_base = gd->ram_top;
 791
 792         video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 793                                  &sunxi_display.depth, &options);
 794         hpd = video_get_option_int(options, "hpd", 1);
 795         edid = video_get_option_int(options, "edid", 1);
 796         sunxi_display.monitor = sunxi_monitor_dvi;
 797         video_get_option_string(options, "monitor", mon, sizeof(mon),
 798                                 sunxi_get_mon_desc(sunxi_display.monitor));
 799         for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
 800                 if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
 801                         sunxi_display.monitor = i;
 802                         break;
 803                 }
 804         }
 805         if (i > SUNXI_MONITOR_LAST)
 806                 printf("Unknown monitor: '%s', falling back to '%s'\n",
 807                        mon, sunxi_get_mon_desc(sunxi_display.monitor));
 808
 809         switch (sunxi_display.monitor) {
 810         case sunxi_monitor_none:
 811                 return NULL;
 812         case sunxi_monitor_dvi:
 813         case sunxi_monitor_hdmi:
 814                 /* Always call hdp_detect, as it also enables clocks, etc. */
 815                 ret = sunxi_hdmi_hpd_detect();
 816                 if (ret) {
 817                         printf("HDMI connected: ");
 818                         if (edid && sunxi_hdmi_edid_get_mode(&custom) == 0)
 819                                 mode = &custom;
 820                         break;
 821                 }
 822                 if (!hpd)
 823                         break; /* User has requested to ignore hpd */
 824
 825                 sunxi_hdmi_shutdown();
 826
 827                 if (lcd_mode[0] == 0)
 828                         return NULL; /* No LCD, bail */
 829
 830                 /* Fall back / through to LCD */
 831                 sunxi_display.monitor = sunxi_monitor_lcd;
 832         case sunxi_monitor_lcd:
 833                 if (lcd_mode[0]) {
 834                         sunxi_display.depth = video_get_params(&custom, lcd_mode);
 835                         mode = &custom;
 836                         break;
 837                 }
 838                 printf("LCD not supported on this board\n");
 839                 return NULL;
 840         case sunxi_monitor_vga:
 841                 printf("VGA not supported on this board\n");
 842                 return NULL;
 843         }
 844
 845         if (mode->vmode != FB_VMODE_NONINTERLACED) {
 846                 printf("Only non-interlaced modes supported, falling back to 1024x768\n");
 847                 mode = &res_mode_init[RES_MODE_1024x768];
 848         } else {
 849                 printf("Setting up a %dx%d %s console\n", mode->xres,
 850                        mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
 851         }
 852
 853         sunxi_display.enabled = true;
 854         sunxi_engines_init();
 855         sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
 856
 857         /*
 858          * These are the only members of this structure that are used. All the
 859          * others are driver specific. There is nothing to decribe pitch or
 860          * stride, but we are lucky with our hw.
 861          */
 862         graphic_device->frameAdrs = gd->fb_base;
 863         graphic_device->gdfIndex = GDF_32BIT_X888RGB;
 864         graphic_device->gdfBytesPP = 4;
 865         graphic_device->winSizeX = mode->xres;
 866         graphic_device->winSizeY = mode->yres;
 867
 868         return graphic_device;
 869 }
 870
 871 /*
 872  * Simplefb support.
 873  */
 874 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
 875 int sunxi_simplefb_setup(void *blob)
 876 {
 877         static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 878         int offset, ret;
 879         const char *pipeline = NULL;
 880
 881         if (!sunxi_display.enabled)
 882                 return 0;
 883
 884         switch (sunxi_display.monitor) {
 885         case sunxi_monitor_none:
 886                 return 0;
 887         case sunxi_monitor_dvi:
 888         case sunxi_monitor_hdmi:
 889                 pipeline = "de_be0-lcd0-hdmi";
 890                 break;
 891         case sunxi_monitor_lcd:
 892                 pipeline = "de_be0-lcd0";
 893                 break;
 894         case sunxi_monitor_vga:
 895                 break;
 896         }
 897
 898         /* Find a prefilled simpefb node, matching out pipeline config */
 899         offset = fdt_node_offset_by_compatible(blob, -1,
 900                                                "allwinner,simple-framebuffer");
 901         while (offset >= 0) {
 902                 ret = fdt_find_string(blob, offset, "allwinner,pipeline",
 903                                       pipeline);
 904                 if (ret == 0)
 905                         break;
 906                 offset = fdt_node_offset_by_compatible(blob, offset,
 907                                                "allwinner,simple-framebuffer");
 908         }
 909         if (offset < 0) {
 910                 eprintf("Cannot setup simplefb: node not found\n");
 911                 return 0; /* Keep older kernels working */
 912         }
 913
 914         ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
 915                         graphic_device->winSizeX, graphic_device->winSizeY,
 916                         graphic_device->winSizeX * graphic_device->gdfBytesPP,
 917                         "x8r8g8b8");
 918         if (ret)
 919                 eprintf("Cannot setup simplefb: Error setting properties\n");
 920
 921         return ret;
 922 }
 923 #endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */