drivers/video/sunxi/sunxi_dw_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Allwinner DW HDMI bridge
   4  *
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  */
   7
   8 #include <common.h>
   9 #include <display.h>
  10 #include <dm.h>
  11 #include <dw_hdmi.h>
  12 #include <edid.h>
  13 #include <time.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/lcdc.h>
  17
  18 struct sunxi_dw_hdmi_priv {
  19         struct dw_hdmi hdmi;
  20         int mux;
  21 };
  22
  23 struct sunxi_hdmi_phy {
  24         u32 pol;
  25         u32 res1[3];
  26         u32 read_en;
  27         u32 unscramble;
  28         u32 res2[2];
  29         u32 ctrl;
  30         u32 unk1;
  31         u32 unk2;
  32         u32 pll;
  33         u32 clk;
  34         u32 unk3;
  35         u32 status;
  36 };
  37
  38 #define HDMI_PHY_OFFS 0x10000
  39
  40 static int sunxi_dw_hdmi_get_divider(uint clock)
  41 {
  42         /*
  43          * Due to missing documentaion of HDMI PHY, we know correct
  44          * settings only for following four PHY dividers. Select one
  45          * based on clock speed.
  46          */
  47         if (clock <= 27000000)
  48                 return 11;
  49         else if (clock <= 74250000)
  50                 return 4;
  51         else if (clock <= 148500000)
  52                 return 2;
  53         else
  54                 return 1;
  55 }
  56
  57 static void sunxi_dw_hdmi_phy_init(void)
  58 {
  59         struct sunxi_hdmi_phy * const phy =
  60                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
  61         unsigned long tmo;
  62         u32 tmp;
  63
  64         /*
  65          * HDMI PHY settings are taken as-is from Allwinner BSP code.
  66          * There is no documentation.
  67          */
  68         writel(0, &phy->ctrl);
  69         setbits_le32(&phy->ctrl, BIT(0));
  70         udelay(5);
  71         setbits_le32(&phy->ctrl, BIT(16));
  72         setbits_le32(&phy->ctrl, BIT(1));
  73         udelay(10);
  74         setbits_le32(&phy->ctrl, BIT(2));
  75         udelay(5);
  76         setbits_le32(&phy->ctrl, BIT(3));
  77         udelay(40);
  78         setbits_le32(&phy->ctrl, BIT(19));
  79         udelay(100);
  80         setbits_le32(&phy->ctrl, BIT(18));
  81         setbits_le32(&phy->ctrl, 7 << 4);
  82
  83         /* Note that Allwinner code doesn't fail in case of timeout */
  84         tmo = timer_get_us() + 2000;
  85         while ((readl(&phy->status) & 0x80) == 0) {
  86                 if (timer_get_us() > tmo) {
  87                         printf("Warning: HDMI PHY init timeout!\n");
  88                         break;
  89                 }
  90         }
  91
  92         setbits_le32(&phy->ctrl, 0xf << 8);
  93         setbits_le32(&phy->ctrl, BIT(7));
  94
  95         writel(0x39dc5040, &phy->pll);
  96         writel(0x80084343, &phy->clk);
  97         udelay(10000);
  98         writel(1, &phy->unk3);
  99         setbits_le32(&phy->pll, BIT(25));
 100         udelay(100000);
 101         tmp = (readl(&phy->status) & 0x1f800) >> 11;
 102         setbits_le32(&phy->pll, BIT(31) | BIT(30));
 103         setbits_le32(&phy->pll, tmp);
 104         writel(0x01FF0F7F, &phy->ctrl);
 105         writel(0x80639000, &phy->unk1);
 106         writel(0x0F81C405, &phy->unk2);
 107
 108         /* enable read access to HDMI controller */
 109         writel(0x54524545, &phy->read_en);
 110         /* descramble register offsets */
 111         writel(0x42494E47, &phy->unscramble);
 112 }
 113
 114 static int sunxi_dw_hdmi_get_plug_in_status(void)
 115 {
 116         struct sunxi_hdmi_phy * const phy =
 117                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 118
 119         return !!(readl(&phy->status) & (1 << 19));
 120 }
 121
 122 static int sunxi_dw_hdmi_wait_for_hpd(void)
 123 {
 124         ulong start;
 125
 126         start = get_timer(0);
 127         do {
 128                 if (sunxi_dw_hdmi_get_plug_in_status())
 129                         return 0;
 130                 udelay(100);
 131         } while (get_timer(start) < 300);
 132
 133         return -1;
 134 }
 135
 136 static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div)
 137 {
 138         struct sunxi_hdmi_phy * const phy =
 139                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 140         int div = sunxi_dw_hdmi_get_divider(clock);
 141         u32 tmp;
 142
 143         /*
 144          * Unfortunately, we don't know much about those magic
 145          * numbers. They are taken from Allwinner BSP driver.
 146          */
 147         switch (div) {
 148         case 1:
 149                 writel(0x30dc5fc0, &phy->pll);
 150                 writel(0x800863C0 | (phy_div - 1), &phy->clk);
 151                 mdelay(10);
 152                 writel(0x00000001, &phy->unk3);
 153                 setbits_le32(&phy->pll, BIT(25));
 154                 mdelay(200);
 155                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 156                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 157                 if (tmp < 0x3d)
 158                         setbits_le32(&phy->pll, tmp + 2);
 159                 else
 160                         setbits_le32(&phy->pll, 0x3f);
 161                 mdelay(100);
 162                 writel(0x01FFFF7F, &phy->ctrl);
 163                 writel(0x8063b000, &phy->unk1);
 164                 writel(0x0F8246B5, &phy->unk2);
 165                 break;
 166         case 2:
 167                 writel(0x39dc5040, &phy->pll);
 168                 writel(0x80084380 | (phy_div - 1), &phy->clk);
 169                 mdelay(10);
 170                 writel(0x00000001, &phy->unk3);
 171                 setbits_le32(&phy->pll, BIT(25));
 172                 mdelay(100);
 173                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 174                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 175                 setbits_le32(&phy->pll, tmp);
 176                 writel(0x01FFFF7F, &phy->ctrl);
 177                 writel(0x8063a800, &phy->unk1);
 178                 writel(0x0F81C485, &phy->unk2);
 179                 break;
 180         case 4:
 181                 writel(0x39dc5040, &phy->pll);
 182                 writel(0x80084340 | (phy_div - 1), &phy->clk);
 183                 mdelay(10);
 184                 writel(0x00000001, &phy->unk3);
 185                 setbits_le32(&phy->pll, BIT(25));
 186                 mdelay(100);
 187                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 188                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 189                 setbits_le32(&phy->pll, tmp);
 190                 writel(0x01FFFF7F, &phy->ctrl);
 191                 writel(0x8063b000, &phy->unk1);
 192                 writel(0x0F81C405, &phy->unk2);
 193                 break;
 194         case 11:
 195                 writel(0x39dc5040, &phy->pll);
 196                 writel(0x80084300 | (phy_div - 1), &phy->clk);
 197                 mdelay(10);
 198                 writel(0x00000001, &phy->unk3);
 199                 setbits_le32(&phy->pll, BIT(25));
 200                 mdelay(100);
 201                 tmp = (readl(&phy->status) & 0x1f800) >> 11;
 202                 setbits_le32(&phy->pll, BIT(31) | BIT(30));
 203                 setbits_le32(&phy->pll, tmp);
 204                 writel(0x01FFFF7F, &phy->ctrl);
 205                 writel(0x8063b000, &phy->unk1);
 206                 writel(0x0F81C405, &phy->unk2);
 207                 break;
 208         }
 209 }
 210
 211 static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div)
 212 {
 213         int value, n, m, div, diff;
 214         int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF;
 215
 216         /*
 217          * Find the lowest divider resulting in a matching clock. If there
 218          * is no match, pick the closest lower clock, as monitors tend to
 219          * not sync to higher frequencies.
 220          */
 221         for (div = 1; div <= 16; div++) {
 222                 int target = clk_khz * div;
 223
 224                 if (target < 192000)
 225                         continue;
 226                 if (target > 912000)
 227                         continue;
 228
 229                 for (m = 1; m <= 16; m++) {
 230                         n = (m * target) / 24000;
 231
 232                         if (n >= 1 && n <= 128) {
 233                                 value = (24000 * n) / m / div;
 234                                 diff = clk_khz - value;
 235                                 if (diff < best_diff) {
 236                                         best_diff = diff;
 237                                         best_m = m;
 238                                         best_n = n;
 239                                         best_div = div;
 240                                 }
 241                         }
 242                 }
 243         }
 244
 245         *phy_div = best_div;
 246
 247         clock_set_pll3_factors(best_m, best_n);
 248         debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
 249               clk_khz, (clock_get_pll3() / 1000) / best_div,
 250               best_n, best_m, best_div);
 251 }
 252
 253 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
 254                                     int bpp)
 255 {
 256         struct sunxi_ccm_reg * const ccm =
 257                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 258         int div = DIV_ROUND_UP(clock_get_pll3(), edid->pixelclock.typ);
 259         struct sunxi_lcdc_reg *lcdc;
 260
 261         if (mux == 0) {
 262                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 263
 264                 /* Reset off */
 265                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
 266
 267                 /* Clock on */
 268                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
 269                 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
 270                        &ccm->lcd0_clk_cfg);
 271         } else {
 272                 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
 273
 274                 /* Reset off */
 275                 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
 276
 277                 /* Clock on */
 278                 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
 279                 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
 280                        &ccm->lcd1_clk_cfg);
 281         }
 282
 283         lcdc_init(lcdc);
 284         lcdc_tcon1_mode_set(lcdc, edid, false, false);
 285         lcdc_enable(lcdc, bpp);
 286 }
 287
 288 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
 289 {
 290         int phy_div;
 291
 292         sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div);
 293         sunxi_dw_hdmi_phy_set(mpixelclock, phy_div);
 294
 295         return 0;
 296 }
 297
 298 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 299 {
 300         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 301
 302         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
 303 }
 304
 305 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
 306                                 const struct display_timing *edid)
 307 {
 308         struct sunxi_hdmi_phy * const phy =
 309                 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
 310         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 311         int ret;
 312
 313         ret = dw_hdmi_enable(&priv->hdmi, edid);
 314         if (ret)
 315                 return ret;
 316
 317         sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
 318
 319         if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
 320                 setbits_le32(&phy->pol, 0x200);
 321
 322         if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
 323                 setbits_le32(&phy->pol, 0x100);
 324
 325         setbits_le32(&phy->ctrl, 0xf << 12);
 326
 327         /*
 328          * This is last hdmi access before boot, so scramble addresses
 329          * again or othwerwise BSP driver won't work. Dummy read is
 330          * needed or otherwise last write doesn't get written correctly.
 331          */
 332         (void)readb(SUNXI_HDMI_BASE);
 333         writel(0, &phy->unscramble);
 334
 335         return 0;
 336 }
 337
 338 static int sunxi_dw_hdmi_probe(struct udevice *dev)
 339 {
 340         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 341         struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
 342         struct sunxi_ccm_reg * const ccm =
 343                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 344         int ret;
 345
 346         /* Set pll3 to 297 MHz */
 347         clock_set_pll3(297000000);
 348
 349         /* Set hdmi parent to pll3 */
 350         clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
 351                         CCM_HDMI_CTRL_PLL3);
 352
 353         /* Set ahb gating to pass */
 354         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
 355         setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
 356         setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
 357         setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
 358
 359         /* Clock on */
 360         setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
 361
 362         sunxi_dw_hdmi_phy_init();
 363
 364         ret = sunxi_dw_hdmi_wait_for_hpd();
 365         if (ret < 0) {
 366                 debug("hdmi can not get hpd signal\n");
 367                 return -1;
 368         }
 369
 370         priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
 371         priv->hdmi.i2c_clk_high = 0xd8;
 372         priv->hdmi.i2c_clk_low = 0xfe;
 373         priv->hdmi.reg_io_width = 1;
 374         priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
 375         priv->mux = uc_plat->source_id;
 376
 377         uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
 378                                      &priv->hdmi.ddc_bus);
 379
 380         dw_hdmi_init(&priv->hdmi);
 381
 382         return 0;
 383 }
 384
 385 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
 386         .read_edid = sunxi_dw_hdmi_read_edid,
 387         .enable = sunxi_dw_hdmi_enable,
 388 };
 389
 390 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
 391         .name   = "sunxi_dw_hdmi",
 392         .id     = UCLASS_DISPLAY,
 393         .ops    = &sunxi_dw_hdmi_ops,
 394         .probe  = sunxi_dw_hdmi_probe,
 395         .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
 396 };
 397
 398 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
 399         .name = "sunxi_dw_hdmi"
 400 };