1 // SPDX-License-Identifier: GPL-2.0+
3 * Allwinner DW HDMI bridge
5 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/lcdc.h>
17 struct sunxi_dw_hdmi_priv {
22 struct sunxi_hdmi_phy {
37 #define HDMI_PHY_OFFS 0x10000
39 static int sunxi_dw_hdmi_get_divider(uint clock)
42 * Due to missing documentaion of HDMI PHY, we know correct
43 * settings only for following four PHY dividers. Select one
44 * based on clock speed.
46 if (clock <= 27000000)
48 else if (clock <= 74250000)
50 else if (clock <= 148500000)
56 static void sunxi_dw_hdmi_phy_init(void)
58 struct sunxi_hdmi_phy * const phy =
59 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
64 * HDMI PHY settings are taken as-is from Allwinner BSP code.
65 * There is no documentation.
67 writel(0, &phy->ctrl);
68 setbits_le32(&phy->ctrl, BIT(0));
70 setbits_le32(&phy->ctrl, BIT(16));
71 setbits_le32(&phy->ctrl, BIT(1));
73 setbits_le32(&phy->ctrl, BIT(2));
75 setbits_le32(&phy->ctrl, BIT(3));
77 setbits_le32(&phy->ctrl, BIT(19));
79 setbits_le32(&phy->ctrl, BIT(18));
80 setbits_le32(&phy->ctrl, 7 << 4);
82 /* Note that Allwinner code doesn't fail in case of timeout */
83 tmo = timer_get_us() + 2000;
84 while ((readl(&phy->status) & 0x80) == 0) {
85 if (timer_get_us() > tmo) {
86 printf("Warning: HDMI PHY init timeout!\n");
91 setbits_le32(&phy->ctrl, 0xf << 8);
92 setbits_le32(&phy->ctrl, BIT(7));
94 writel(0x39dc5040, &phy->pll);
95 writel(0x80084343, &phy->clk);
97 writel(1, &phy->unk3);
98 setbits_le32(&phy->pll, BIT(25));
100 tmp = (readl(&phy->status) & 0x1f800) >> 11;
101 setbits_le32(&phy->pll, BIT(31) | BIT(30));
102 setbits_le32(&phy->pll, tmp);
103 writel(0x01FF0F7F, &phy->ctrl);
104 writel(0x80639000, &phy->unk1);
105 writel(0x0F81C405, &phy->unk2);
107 /* enable read access to HDMI controller */
108 writel(0x54524545, &phy->read_en);
109 /* descramble register offsets */
110 writel(0x42494E47, &phy->unscramble);
113 static int sunxi_dw_hdmi_get_plug_in_status(void)
115 struct sunxi_hdmi_phy * const phy =
116 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
118 return !!(readl(&phy->status) & (1 << 19));
121 static int sunxi_dw_hdmi_wait_for_hpd(void)
125 start = get_timer(0);
127 if (sunxi_dw_hdmi_get_plug_in_status())
130 } while (get_timer(start) < 300);
135 static void sunxi_dw_hdmi_phy_set(uint clock)
137 struct sunxi_hdmi_phy * const phy =
138 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
139 int div = sunxi_dw_hdmi_get_divider(clock);
143 * Unfortunately, we don't know much about those magic
144 * numbers. They are taken from Allwinner BSP driver.
148 writel(0x30dc5fc0, &phy->pll);
149 writel(0x800863C0, &phy->clk);
151 writel(0x00000001, &phy->unk3);
152 setbits_le32(&phy->pll, BIT(25));
154 tmp = (readl(&phy->status) & 0x1f800) >> 11;
155 setbits_le32(&phy->pll, BIT(31) | BIT(30));
157 setbits_le32(&phy->pll, tmp + 2);
159 setbits_le32(&phy->pll, 0x3f);
161 writel(0x01FFFF7F, &phy->ctrl);
162 writel(0x8063b000, &phy->unk1);
163 writel(0x0F8246B5, &phy->unk2);
166 writel(0x39dc5040, &phy->pll);
167 writel(0x80084381, &phy->clk);
169 writel(0x00000001, &phy->unk3);
170 setbits_le32(&phy->pll, BIT(25));
172 tmp = (readl(&phy->status) & 0x1f800) >> 11;
173 setbits_le32(&phy->pll, BIT(31) | BIT(30));
174 setbits_le32(&phy->pll, tmp);
175 writel(0x01FFFF7F, &phy->ctrl);
176 writel(0x8063a800, &phy->unk1);
177 writel(0x0F81C485, &phy->unk2);
180 writel(0x39dc5040, &phy->pll);
181 writel(0x80084343, &phy->clk);
183 writel(0x00000001, &phy->unk3);
184 setbits_le32(&phy->pll, BIT(25));
186 tmp = (readl(&phy->status) & 0x1f800) >> 11;
187 setbits_le32(&phy->pll, BIT(31) | BIT(30));
188 setbits_le32(&phy->pll, tmp);
189 writel(0x01FFFF7F, &phy->ctrl);
190 writel(0x8063b000, &phy->unk1);
191 writel(0x0F81C405, &phy->unk2);
194 writel(0x39dc5040, &phy->pll);
195 writel(0x8008430a, &phy->clk);
197 writel(0x00000001, &phy->unk3);
198 setbits_le32(&phy->pll, BIT(25));
200 tmp = (readl(&phy->status) & 0x1f800) >> 11;
201 setbits_le32(&phy->pll, BIT(31) | BIT(30));
202 setbits_le32(&phy->pll, tmp);
203 writel(0x01FFFF7F, &phy->ctrl);
204 writel(0x8063b000, &phy->unk1);
205 writel(0x0F81C405, &phy->unk2);
210 static void sunxi_dw_hdmi_pll_set(uint clk_khz)
212 int value, n, m, div = 0, diff;
213 int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
215 div = sunxi_dw_hdmi_get_divider(clk_khz * 1000);
218 * Find the lowest divider resulting in a matching clock. If there
219 * is no match, pick the closest lower clock, as monitors tend to
220 * not sync to higher frequencies.
222 for (m = 1; m <= 16; m++) {
223 n = (m * div * clk_khz) / 24000;
225 if ((n >= 1) && (n <= 128)) {
226 value = (24000 * n) / m / div;
227 diff = clk_khz - value;
228 if (diff < best_diff) {
236 clock_set_pll3_factors(best_m, best_n);
237 debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
238 clk_khz, (clock_get_pll3() / 1000) / div,
239 best_n, best_m, div);
242 static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
245 struct sunxi_ccm_reg * const ccm =
246 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
247 int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
248 struct sunxi_lcdc_reg *lcdc;
251 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
254 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
257 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
258 writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
261 lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
264 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
267 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
268 writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
273 lcdc_tcon1_mode_set(lcdc, edid, false, false);
274 lcdc_enable(lcdc, bpp);
277 static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
279 sunxi_dw_hdmi_pll_set(mpixelclock/1000);
280 sunxi_dw_hdmi_phy_set(mpixelclock);
285 static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
287 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
289 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
292 static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
293 const struct display_timing *edid)
295 struct sunxi_hdmi_phy * const phy =
296 (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
297 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
300 ret = dw_hdmi_enable(&priv->hdmi, edid);
304 sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
306 if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
307 setbits_le32(&phy->pol, 0x200);
309 if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
310 setbits_le32(&phy->pol, 0x100);
312 setbits_le32(&phy->ctrl, 0xf << 12);
315 * This is last hdmi access before boot, so scramble addresses
316 * again or othwerwise BSP driver won't work. Dummy read is
317 * needed or otherwise last write doesn't get written correctly.
319 (void)readb(SUNXI_HDMI_BASE);
320 writel(0, &phy->unscramble);
325 static int sunxi_dw_hdmi_probe(struct udevice *dev)
327 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
328 struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
329 struct sunxi_ccm_reg * const ccm =
330 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
333 /* Set pll3 to 297 MHz */
334 clock_set_pll3(297000000);
336 /* Set hdmi parent to pll3 */
337 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
340 /* Set ahb gating to pass */
341 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
342 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
343 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
344 setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
347 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
349 sunxi_dw_hdmi_phy_init();
351 ret = sunxi_dw_hdmi_wait_for_hpd();
353 debug("hdmi can not get hpd signal\n");
357 priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
358 priv->hdmi.i2c_clk_high = 0xd8;
359 priv->hdmi.i2c_clk_low = 0xfe;
360 priv->hdmi.reg_io_width = 1;
361 priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
362 priv->mux = uc_plat->source_id;
364 dw_hdmi_init(&priv->hdmi);
369 static const struct dm_display_ops sunxi_dw_hdmi_ops = {
370 .read_edid = sunxi_dw_hdmi_read_edid,
371 .enable = sunxi_dw_hdmi_enable,
374 U_BOOT_DRIVER(sunxi_dw_hdmi) = {
375 .name = "sunxi_dw_hdmi",
376 .id = UCLASS_DISPLAY,
377 .ops = &sunxi_dw_hdmi_ops,
378 .probe = sunxi_dw_hdmi_probe,
379 .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
382 U_BOOT_DEVICE(sunxi_dw_hdmi) = {
383 .name = "sunxi_dw_hdmi"