drivers/video/rockchip/rk_hdmi.c

   1 /*
   2  * Copyright (c) 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <dw_hdmi.h>
  13 #include <edid.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/gpio.h>
  17 #include <asm/hardware.h>
  18 #include <asm/io.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/grf_rk3288.h>
  21 #include <power/regulator.h>
  22
  23 struct rk_hdmi_priv {
  24         struct dw_hdmi hdmi;
  25         struct rk3288_grf *grf;
  26 };
  27
  28 static const struct hdmi_phy_config rockchip_phy_config[] = {
  29         {
  30                 .mpixelclock = 74250000,
  31                 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
  32         }, {
  33                 .mpixelclock = 148500000,
  34                 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
  35         }, {
  36                 .mpixelclock = 297000000,
  37                 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
  38         }, {
  39                 .mpixelclock = 584000000,
  40                 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
  41         }, {
  42                 .mpixelclock = ~0ul,
  43                 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
  44         }
  45 };
  46
  47 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
  48         {
  49                 .mpixelclock = 40000000,
  50                 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
  51         }, {
  52                 .mpixelclock = 65000000,
  53                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  54         }, {
  55                 .mpixelclock = 66000000,
  56                 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
  57         }, {
  58                 .mpixelclock = 83500000,
  59                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  60         }, {
  61                 .mpixelclock = 146250000,
  62                 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
  63         }, {
  64                 .mpixelclock = 148500000,
  65                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  66         }, {
  67                 .mpixelclock = 272000000,
  68                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  69         }, {
  70                 .mpixelclock = 340000000,
  71                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  72         }, {
  73                 .mpixelclock = ~0ul,
  74                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  75         }
  76 };
  77
  78 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  79 {
  80         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  81
  82         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  83 }
  84
  85 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
  86                           const struct display_timing *edid)
  87 {
  88         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  89
  90         return dw_hdmi_enable(&priv->hdmi, edid);
  91 }
  92
  93 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
  94 {
  95         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  96         struct dw_hdmi *hdmi = &priv->hdmi;
  97
  98         hdmi->ioaddr = (ulong)devfdt_get_addr(dev);
  99         hdmi->mpll_cfg = rockchip_mpll_cfg;
 100         hdmi->phy_cfg = rockchip_phy_config;
 101         hdmi->i2c_clk_high = 0x7a;
 102         hdmi->i2c_clk_low = 0x8d;
 103
 104         /*
 105          * TODO(sjg@chromium.org): The above values don't work - these ones
 106          * work better, but generate lots of errors in the data.
 107          */
 108         hdmi->i2c_clk_high = 0x0d;
 109         hdmi->i2c_clk_low = 0x0d;
 110         hdmi->reg_io_width = 4;
 111         hdmi->phy_set = dw_hdmi_phy_cfg;
 112
 113         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 114
 115         return 0;
 116 }
 117
 118 static int rk_hdmi_probe(struct udevice *dev)
 119 {
 120         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 121         struct rk_hdmi_priv *priv = dev_get_priv(dev);
 122         struct dw_hdmi *hdmi = &priv->hdmi;
 123         struct udevice *reg;
 124         struct clk clk;
 125         int ret;
 126         int vop_id = uc_plat->source_id;
 127
 128         ret = clk_get_by_index(dev, 0, &clk);
 129         if (ret >= 0) {
 130                 ret = clk_set_rate(&clk, 0);
 131                 clk_free(&clk);
 132         }
 133         if (ret) {
 134                 debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret);
 135                 return ret;
 136         }
 137
 138         /*
 139          * Configure the maximum clock to permit whatever resolution the
 140          * monitor wants
 141          */
 142         ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 143         if (ret >= 0) {
 144                 ret = clk_set_rate(&clk, 384000000);
 145                 clk_free(&clk);
 146         }
 147         if (ret < 0) {
 148                 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
 149                       __func__, uc_plat->src_dev->name, ret);
 150                 return ret;
 151         }
 152
 153         ret = regulator_get_by_platname("vcc50_hdmi", &reg);
 154         if (!ret)
 155                 ret = regulator_set_enable(reg, true);
 156         if (ret)
 157                 debug("%s: Cannot set regulator vcc50_hdmi\n", __func__);
 158
 159         /* hdmi source select hdmi controller */
 160         rk_setreg(&priv->grf->soc_con6, 1 << 15);
 161
 162         /* hdmi data from vop id */
 163         rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
 164                      (vop_id == 1) ? (1 << 4) : 0);
 165
 166         ret = dw_hdmi_phy_wait_for_hpd(hdmi);
 167         if (ret < 0) {
 168                 debug("hdmi can not get hpd signal\n");
 169                 return -1;
 170         }
 171
 172         dw_hdmi_init(hdmi);
 173         dw_hdmi_phy_init(hdmi);
 174
 175         return 0;
 176 }
 177
 178 static const struct dm_display_ops rk_hdmi_ops = {
 179         .read_edid = rk_hdmi_read_edid,
 180         .enable = rk_hdmi_enable,
 181 };
 182
 183 static const struct udevice_id rk_hdmi_ids[] = {
 184         { .compatible = "rockchip,rk3288-dw-hdmi" },
 185         { }
 186 };
 187
 188 U_BOOT_DRIVER(hdmi_rockchip) = {
 189         .name   = "hdmi_rockchip",
 190         .id     = UCLASS_DISPLAY,
 191         .of_match = rk_hdmi_ids,
 192         .ops    = &rk_hdmi_ops,
 193         .ofdata_to_platdata     = rk_hdmi_ofdata_to_platdata,
 194         .probe  = rk_hdmi_probe,
 195         .priv_auto_alloc_size    = sizeof(struct rk_hdmi_priv),
 196 };