1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
4 * Copyright (c) 2015 Google, Inc
5 * Copyright 2014 Rockchip Inc.
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/hardware.h>
21 #include "rk_vop.h" /* for rk_vop_probe_regulators */
23 static const struct hdmi_phy_config rockchip_phy_config[] = {
25 .mpixelclock = 74250000,
26 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
28 .mpixelclock = 148500000,
29 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
31 .mpixelclock = 297000000,
32 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
34 .mpixelclock = 584000000,
35 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
38 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
42 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
44 .mpixelclock = 40000000,
45 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
47 .mpixelclock = 65000000,
48 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
50 .mpixelclock = 66000000,
51 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
53 .mpixelclock = 83500000,
54 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
56 .mpixelclock = 146250000,
57 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
59 .mpixelclock = 148500000,
60 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
62 .mpixelclock = 272000000,
63 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
65 .mpixelclock = 340000000,
66 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
69 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
73 int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
75 struct rk_hdmi_priv *priv = dev_get_priv(dev);
77 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
80 int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
82 struct rk_hdmi_priv *priv = dev_get_priv(dev);
83 struct dw_hdmi *hdmi = &priv->hdmi;
85 hdmi->ioaddr = (ulong)dev_read_addr(dev);
86 hdmi->mpll_cfg = rockchip_mpll_cfg;
87 hdmi->phy_cfg = rockchip_phy_config;
89 /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
91 hdmi->reg_io_width = 4;
92 hdmi->phy_set = dw_hdmi_phy_cfg;
94 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
96 uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus",
102 void rk_hdmi_probe_regulators(struct udevice *dev,
103 const char * const *names, int cnt)
105 rk_vop_probe_regulators(dev, names, cnt);
108 int rk_hdmi_probe(struct udevice *dev)
110 struct rk_hdmi_priv *priv = dev_get_priv(dev);
111 struct dw_hdmi *hdmi = &priv->hdmi;
114 ret = dw_hdmi_phy_wait_for_hpd(hdmi);
116 debug("hdmi can not get hpd signal\n");
121 dw_hdmi_phy_init(hdmi);