drivers/video/rockchip/rk_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
   4  * Copyright (c) 2015 Google, Inc
   5  * Copyright 2014 Rockchip Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <display.h>
  11 #include <dm.h>
  12 #include <dw_hdmi.h>
  13 #include <edid.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/gpio.h>
  17 #include <asm/io.h>
  18 #include <asm/arch-rockchip/clock.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include "rk_hdmi.h"
  21 #include "rk_vop.h" /* for rk_vop_probe_regulators */
  22
  23 static const struct hdmi_phy_config rockchip_phy_config[] = {
  24         {
  25                 .mpixelclock = 74250000,
  26                 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
  27         }, {
  28                 .mpixelclock = 148500000,
  29                 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
  30         }, {
  31                 .mpixelclock = 297000000,
  32                 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
  33         }, {
  34                 .mpixelclock = 584000000,
  35                 .sym_ctr = 0x8039, .term = 0x0000, .vlev_ctr = 0x019d,
  36         }, {
  37                 .mpixelclock = ~0ul,
  38                 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
  39         }
  40 };
  41
  42 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
  43         {
  44                 .mpixelclock = 40000000,
  45                 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
  46         }, {
  47                 .mpixelclock = 65000000,
  48                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  49         }, {
  50                 .mpixelclock = 66000000,
  51                 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
  52         }, {
  53                 .mpixelclock = 83500000,
  54                 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
  55         }, {
  56                 .mpixelclock = 146250000,
  57                 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
  58         }, {
  59                 .mpixelclock = 148500000,
  60                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  61         }, {
  62                 .mpixelclock = 272000000,
  63                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  64         }, {
  65                 .mpixelclock = 340000000,
  66                 .cpce = 0x0040, .gmp = 0x0003, .curr = 0x0000,
  67         }, {
  68                 .mpixelclock = ~0ul,
  69                 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
  70         }
  71 };
  72
  73 int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
  74 {
  75         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  76
  77         return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
  78 }
  79
  80 int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
  81 {
  82         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  83         struct dw_hdmi *hdmi = &priv->hdmi;
  84
  85         hdmi->ioaddr = (ulong)dev_read_addr(dev);
  86         hdmi->mpll_cfg = rockchip_mpll_cfg;
  87         hdmi->phy_cfg = rockchip_phy_config;
  88
  89         /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
  90
  91         hdmi->reg_io_width = 4;
  92         hdmi->phy_set = dw_hdmi_phy_cfg;
  93
  94         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  95
  96         return 0;
  97 }
  98
  99 void rk_hdmi_probe_regulators(struct udevice *dev,
 100                               const char * const *names, int cnt)
 101 {
 102         rk_vop_probe_regulators(dev, names, cnt);
 103 }
 104
 105 int rk_hdmi_probe(struct udevice *dev)
 106 {
 107         struct rk_hdmi_priv *priv = dev_get_priv(dev);
 108         struct dw_hdmi *hdmi = &priv->hdmi;
 109         int ret;
 110
 111         ret = dw_hdmi_phy_wait_for_hpd(hdmi);
 112         if (ret < 0) {
 113                 debug("hdmi can not get hpd signal\n");
 114                 return -1;
 115         }
 116
 117         dw_hdmi_init(hdmi);
 118         dw_hdmi_phy_init(hdmi);
 119
 120         return 0;
 121 }