2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
5 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/edp_rk3288.h>
20 #include <asm/arch/grf_rk3288.h>
21 #include <dt-bindings/clock/rk3288-cru.h>
25 #define DP_LINK_STATUS_SIZE 6
27 static const char * const voltage_names[] = {
28 "0.4V", "0.6V", "0.8V", "1.2V"
30 static const char * const pre_emph_names[] = {
31 "0dB", "3.5dB", "6dB", "9.5dB"
34 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
35 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
38 struct rk3288_edp *regs;
39 struct rk3288_grf *grf;
40 struct udevice *panel;
41 struct link_train link_train;
45 static void rk_edp_init_refclk(struct rk3288_edp *regs)
47 writel(SEL_24M, ®s->analog_ctl_2);
48 writel(REF_CLK_24M, ®s->pll_reg_1);
50 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
51 V2L_CUR_SEL_1MA, ®s->pll_reg_2);
53 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
54 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
57 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
58 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
61 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, ®s->ssc_reg);
63 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
64 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
67 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
70 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
73 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
77 static void rk_edp_init_interrupt(struct rk3288_edp *regs)
79 /* Set interrupt pin assertion polarity as high */
80 writel(INT_POL, ®s->int_ctl);
82 /* Clear pending registers */
83 writel(0xff, ®s->common_int_sta_1);
84 writel(0x4f, ®s->common_int_sta_2);
85 writel(0xff, ®s->common_int_sta_3);
86 writel(0x27, ®s->common_int_sta_4);
87 writel(0x7f, ®s->dp_int_sta);
89 /* 0:mask,1: unmask */
90 writel(0x00, ®s->common_int_mask_1);
91 writel(0x00, ®s->common_int_mask_2);
92 writel(0x00, ®s->common_int_mask_3);
93 writel(0x00, ®s->common_int_mask_4);
94 writel(0x00, ®s->int_sta_mask);
97 static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
99 clrbits_le32(®s->func_en_1, SW_FUNC_EN_N);
102 static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
106 val = readl(®s->dp_debug_ctl);
108 return val & PLL_LOCK;
111 static int rk_edp_init_analog_func(struct rk3288_edp *regs)
115 writel(0x00, ®s->dp_pd);
116 writel(PLL_LOCK_CHG, ®s->common_int_sta_1);
118 clrbits_le32(®s->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
120 start = get_timer(0);
121 while (!rk_edp_get_pll_locked(regs)) {
122 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
123 printf("%s: PLL is not locked\n", __func__);
128 /* Enable Serdes FIFO function and Link symbol clock domain module */
129 clrbits_le32(®s->func_en_2, SERDES_FIFO_FUNC_EN_N |
130 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
136 static void rk_edp_init_aux(struct rk3288_edp *regs)
138 /* Clear inerrupts related to AUX channel */
139 writel(AUX_FUNC_EN_N, ®s->dp_int_sta);
141 /* Disable AUX channel module */
142 setbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
144 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
145 writel(DEFER_CTRL_EN | DEFER_COUNT(1), ®s->aux_ch_defer_dtl);
147 /* Enable AUX channel module */
148 clrbits_le32(®s->func_en_2, AUX_FUNC_EN_N);
151 static int rk_edp_aux_enable(struct rk3288_edp *regs)
155 setbits_le32(®s->aux_ch_ctl_2, AUX_EN);
156 start = get_timer(0);
158 if (!(readl(®s->aux_ch_ctl_2) & AUX_EN))
160 } while (get_timer(start) < 20);
165 static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
169 start = get_timer(0);
170 while (!(readl(®s->dp_int_sta) & RPLY_RECEIV)) {
171 if (get_timer(start) > 10)
175 writel(RPLY_RECEIV, ®s->dp_int_sta);
180 static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
184 /* Enable AUX CH operation */
185 ret = rk_edp_aux_enable(regs);
187 debug("AUX CH enable timeout!\n");
191 /* Is AUX CH command reply received? */
192 if (rk_edp_is_aux_reply(regs)) {
193 debug("AUX CH command reply failed!\n");
197 /* Clear interrupt source for AUX CH access error */
198 val = readl(®s->dp_int_sta);
200 writel(AUX_ERR, ®s->dp_int_sta);
204 /* Check AUX CH error access status */
205 val = readl(®s->dp_int_sta);
206 if (val & AUX_STATUS_MASK) {
207 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
214 static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
215 unsigned int val_addr, u8 *in_data,
217 enum dpcd_request request)
226 len = min(length, 16U);
227 for (try_times = 0; try_times < 10; try_times++) {
229 /* Clear AUX CH data buffer */
230 writel(BUF_CLR, ®s->buf_data_ctl);
232 /* Select DPCD device address */
233 writel(AUX_ADDR_7_0(val_addr), ®s->aux_addr_7_0);
234 writel(AUX_ADDR_15_8(val_addr), ®s->aux_addr_15_8);
235 writel(AUX_ADDR_19_16(val_addr), ®s->aux_addr_19_16);
238 * Set DisplayPort transaction and read 1 byte
239 * If bit 3 is 1, DisplayPort transaction.
240 * If Bit 3 is 0, I2C transaction.
242 if (request == DPCD_WRITE) {
243 val = AUX_LENGTH(len) |
244 AUX_TX_COMM_DP_TRANSACTION |
246 for (i = 0; i < len; i++)
247 writel(*data++, ®s->buf_data[i]);
249 val = AUX_LENGTH(len) |
250 AUX_TX_COMM_DP_TRANSACTION |
253 writel(val, ®s->aux_ch_ctl_1);
255 /* Start AUX transaction */
256 ret = rk_edp_start_aux_transaction(regs);
260 printf("read dpcd Aux Transaction fail!\n");
266 if (request == DPCD_READ) {
267 for (i = 0; i < len; i++)
268 *data++ = (u8)readl(®s->buf_data[i]);
279 static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
282 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
285 static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
288 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
292 static int rk_edp_link_power_up(struct rk_edp_priv *edp)
297 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
298 if (edp->link_train.revision < 0x11)
301 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
305 value &= ~DP_SET_POWER_MASK;
306 value |= DP_SET_POWER_D0;
308 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
313 * According to the DP 1.1 specification, a "Sink Device must exit the
314 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
315 * Control Field" (register 0x600).
322 static int rk_edp_link_configure(struct rk_edp_priv *edp)
326 values[0] = edp->link_train.link_rate;
327 values[1] = edp->link_train.lane_count;
329 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
333 static void rk_edp_set_link_training(struct rk_edp_priv *edp,
334 const u8 *training_values)
338 for (i = 0; i < edp->link_train.lane_count; i++)
339 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
342 static u8 edp_link_status(const u8 *link_status, int r)
344 return link_status[r - DPCD_LANE0_1_STATUS];
347 static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
350 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
351 DP_LINK_STATUS_SIZE);
354 static u8 edp_get_lane_status(const u8 *link_status, int lane)
356 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
357 int s = (lane & 1) * 4;
358 u8 l = edp_link_status(link_status, i);
360 return (l >> s) & 0xf;
363 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
368 for (lane = 0; lane < lane_count; lane++) {
369 lane_status = edp_get_lane_status(link_status, lane);
370 if ((lane_status & DP_LANE_CR_DONE) == 0)
377 static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
383 lane_align = edp_link_status(link_status,
384 DPCD_LANE_ALIGN_STATUS_UPDATED);
385 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
387 for (lane = 0; lane < lane_count; lane++) {
388 lane_status = edp_get_lane_status(link_status, lane);
389 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
396 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
398 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
399 int s = ((lane & 1) ?
400 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
401 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
402 u8 l = edp_link_status(link_status, i);
404 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
407 static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
410 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
411 int s = ((lane & 1) ?
412 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
413 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
414 u8 l = edp_link_status(link_status, i);
416 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
419 static void edp_get_adjust_train(const u8 *link_status, int lane_count,
426 for (lane = 0; lane < lane_count; lane++) {
429 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
430 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
433 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
435 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
436 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
444 if (v >= DP_VOLTAGE_MAX)
445 v |= DP_TRAIN_MAX_SWING_REACHED;
447 if (p >= DP_PRE_EMPHASIS_MAX)
448 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
450 debug("using signal parameters: voltage %s pre_emph %s\n",
451 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
452 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
453 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
454 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
456 for (lane = 0; lane < 4; lane++)
457 train_set[lane] = v | p;
460 static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
462 struct rk3288_edp *regs = edp->regs;
464 uint voltage, tries = 0;
465 u8 status[DP_LINK_STATUS_SIZE];
469 value = DP_TRAINING_PATTERN_1;
470 writel(value, ®s->dp_training_ptn_set);
471 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
474 memset(edp->train_set, '\0', sizeof(edp->train_set));
476 /* clock recovery loop */
482 rk_edp_set_link_training(edp, edp->train_set);
483 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
485 edp->link_train.lane_count);
491 ret = rk_edp_dpcd_read_link_status(edp, status);
493 printf("displayport link status failed, ret=%d\n", ret);
497 clock_recovery = rk_edp_clock_recovery(status,
498 edp->link_train.lane_count);
502 for (i = 0; i < edp->link_train.lane_count; i++) {
503 if ((edp->train_set[i] &
504 DP_TRAIN_MAX_SWING_REACHED) == 0)
507 if (i == edp->link_train.lane_count) {
508 printf("clock recovery reached max voltage\n");
512 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
514 if (++tries == MAX_CR_LOOP) {
515 printf("clock recovery tried 5 times\n");
522 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
524 /* Compute new train_set as requested by sink */
525 edp_get_adjust_train(status, edp->link_train.lane_count,
528 if (clock_recovery) {
529 printf("clock recovery failed: %d\n", clock_recovery);
530 return clock_recovery;
532 debug("clock recovery at voltage %d pre-emphasis %d\n",
533 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
534 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
535 DP_TRAIN_PRE_EMPHASIS_SHIFT);
540 static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
542 struct rk3288_edp *regs = edp->regs;
546 u8 status[DP_LINK_STATUS_SIZE];
549 value = DP_TRAINING_PATTERN_2;
550 writel(value, ®s->dp_training_ptn_set);
551 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
555 /* channel equalization loop */
557 for (tries = 0; tries < 5; tries++) {
558 rk_edp_set_link_training(edp, edp->train_set);
561 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
562 printf("displayport link status failed\n");
566 channel_eq = rk_edp_channel_eq(status,
567 edp->link_train.lane_count);
570 edp_get_adjust_train(status, edp->link_train.lane_count,
575 printf("channel eq failed, ret=%d\n", channel_eq);
579 debug("channel eq at voltage %d pre-emphasis %d\n",
580 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
581 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
582 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
587 static int rk_edp_init_training(struct rk_edp_priv *edp)
592 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
597 edp->link_train.revision = values[0];
598 edp->link_train.link_rate = values[1];
599 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
601 debug("max link rate:%d.%dGps max number of lanes:%d\n",
602 edp->link_train.link_rate * 27 / 100,
603 edp->link_train.link_rate * 27 % 100,
604 edp->link_train.lane_count);
606 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
607 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
608 debug("Rx Max Link Rate is abnormal :%x\n",
609 edp->link_train.link_rate);
613 if (edp->link_train.lane_count == 0) {
614 debug("Rx Max Lane count is abnormal :%x\n",
615 edp->link_train.lane_count);
619 ret = rk_edp_link_power_up(edp);
623 return rk_edp_link_configure(edp);
626 static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
632 /* Set link rate and count as you want to establish */
633 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
634 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
636 ret = rk_edp_link_train_cr(edp);
639 ret = rk_edp_link_train_ce(edp);
643 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
644 start = get_timer(0);
646 val = readl(&edp->regs->dp_hw_link_training);
647 if (!(val & HW_LT_EN))
649 } while (get_timer(start) < 10);
651 if (val & HW_LT_ERR_CODE_MASK) {
652 printf("edp hw link training error: %d\n",
653 val >> HW_LT_ERR_CODE_SHIFT);
660 static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
661 unsigned int device_addr,
662 unsigned int val_addr)
666 /* Set EDID device address */
667 writel(device_addr, ®s->aux_addr_7_0);
668 writel(0x0, ®s->aux_addr_15_8);
669 writel(0x0, ®s->aux_addr_19_16);
671 /* Set offset from base address of EDID device */
672 writel(val_addr, ®s->buf_data[0]);
675 * Set I2C transaction and write address
676 * If bit 3 is 1, DisplayPort transaction.
677 * If Bit 3 is 0, I2C transaction.
679 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
680 AUX_TX_COMM_WRITE, ®s->aux_ch_ctl_1);
682 /* Start AUX transaction */
683 ret = rk_edp_start_aux_transaction(regs);
685 debug("select_i2c_device Aux Transaction fail!\n");
692 static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
693 unsigned int val_addr, unsigned int count, u8 edid[])
697 unsigned int cur_data_idx;
698 unsigned int defer = 0;
701 for (i = 0; i < count; i += 16) {
702 for (j = 0; j < 10; j++) { /* try 10 times */
703 /* Clear AUX CH data buffer */
704 writel(BUF_CLR, ®s->buf_data_ctl);
706 /* Set normal AUX CH command */
707 clrbits_le32(®s->aux_ch_ctl_2, ADDR_ONLY);
710 * If Rx sends defer, Tx sends only reads
711 * request without sending addres
714 ret = rk_edp_select_i2c_device(regs,
722 * Set I2C transaction and write data
723 * If bit 3 is 1, DisplayPort transaction.
724 * If Bit 3 is 0, I2C transaction.
726 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
727 AUX_TX_COMM_READ, ®s->aux_ch_ctl_1);
729 /* Start AUX transaction */
730 ret = rk_edp_start_aux_transaction(regs);
734 debug("Aux Transaction fail!\n");
738 /* Check if Rx sends defer */
739 val = readl(®s->aux_rx_comm);
740 if (val == AUX_RX_COMM_AUX_DEFER ||
741 val == AUX_RX_COMM_I2C_DEFER) {
742 debug("Defer: %d\n\n", val);
750 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
751 val = readl(®s->buf_data[cur_data_idx]);
752 edid[i + cur_data_idx] = (u8)val;
759 static int rk_edp_set_link_train(struct rk_edp_priv *edp)
763 ret = rk_edp_init_training(edp);
765 printf("DP LT init failed!\n");
769 ret = rk_edp_hw_link_training(edp);
776 static void rk_edp_init_video(struct rk3288_edp *regs)
778 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
779 ®s->common_int_sta_1);
780 writel(CHA_CRI(4) | CHA_CTRL, ®s->sys_ctl_2);
781 writel(VID_HRES_TH(2) | VID_VRES_TH(0), ®s->video_ctl_8);
784 static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
786 clrbits_le32(®s->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
789 static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
790 enum clock_recovery_m_value_type type,
794 if (type == REGISTER_M) {
795 setbits_le32(®s->sys_ctl_4, FIX_M_VID);
796 writel(m_value & 0xff, ®s->m_vid_0);
797 writel((m_value >> 8) & 0xff, ®s->m_vid_1);
798 writel((m_value >> 16) & 0xff, ®s->m_vid_2);
800 writel(n_value & 0xf, ®s->n_vid_0);
801 writel((n_value >> 8) & 0xff, ®s->n_vid_1);
802 writel((n_value >> 16) & 0xff, ®s->n_vid_2);
804 clrbits_le32(®s->sys_ctl_4, FIX_M_VID);
806 writel(0x00, ®s->n_vid_0);
807 writel(0x80, ®s->n_vid_1);
808 writel(0x00, ®s->n_vid_2);
812 static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
817 start = get_timer(0);
819 val = readl(®s->sys_ctl_1);
821 /* must write value to update DET_STA bit status */
822 writel(val, ®s->sys_ctl_1);
823 val = readl(®s->sys_ctl_1);
824 if (!(val & DET_STA))
827 val = readl(®s->sys_ctl_2);
829 /* must write value to update CHA_STA bit status */
830 writel(val, ®s->sys_ctl_2);
831 val = readl(®s->sys_ctl_2);
832 if (!(val & CHA_STA))
835 } while (get_timer(start) < 100);
840 static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
845 start = get_timer(0);
847 val = readl(&edp->regs->sys_ctl_3);
849 /* must write value to update STRM_VALID bit status */
850 writel(val, &edp->regs->sys_ctl_3);
852 val = readl(&edp->regs->sys_ctl_3);
853 if (!(val & STRM_VALID))
855 } while (get_timer(start) < 100);
860 static int rk_edp_config_video(struct rk_edp_priv *edp)
864 rk_edp_config_video_slave_mode(edp->regs);
866 if (!rk_edp_get_pll_locked(edp->regs)) {
867 debug("PLL is not locked yet.\n");
871 ret = rk_edp_is_video_stream_clock_on(edp->regs);
875 /* Set to use the register calculated M/N video */
876 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
878 /* For video bist, Video timing must be generated by register */
879 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
881 /* Disable video mute */
882 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
884 /* Enable video at next frame */
885 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
887 return rk_edp_is_video_stream_on(edp);
890 static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
892 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
895 static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
899 val = readl(&edp->regs->sys_ctl_3);
900 if (val & HPD_STATUS)
907 * support edp HPD function
908 * some hardware version do not support edp hdp,
909 * we use 200ms to try to get the hpd single now,
910 * if we can not get edp hpd single, it will delay 200ms,
911 * also meet the edp power timing request, to compatible
912 * all of the hardware version
914 static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
918 start = get_timer(0);
920 if (rockchip_edp_get_plug_in_status(edp))
923 } while (get_timer(start) < 200);
925 debug("do not get hpd single, force hpd\n");
926 rockchip_edp_force_hpd(edp);
929 static int rk_edp_enable(struct udevice *dev, int panel_bpp,
930 const struct display_timing *edid)
932 struct rk_edp_priv *priv = dev_get_priv(dev);
935 ret = rk_edp_set_link_train(priv);
937 printf("link train failed!\n");
941 rk_edp_init_video(priv->regs);
942 ret = rk_edp_config_video(priv);
944 printf("config video failed\n");
947 ret = panel_enable_backlight(priv->panel);
949 debug("%s: backlight error: %d\n", __func__, ret);
956 static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
958 struct rk_edp_priv *priv = dev_get_priv(dev);
959 u32 edid_size = EDID_LENGTH;
963 for (i = 0; i < 3; i++) {
964 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
965 EDID_LENGTH, &buf[EDID_HEADER]);
967 debug("EDID read failed\n");
972 * check if the EDID has an extension flag, and read additional
973 * EDID data if needed
975 if (buf[EDID_EXTENSION_FLAG]) {
976 edid_size += EDID_LENGTH;
977 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
978 EDID_LENGTH, EDID_LENGTH,
981 debug("EDID Read failed!\n");
988 /* After 3 attempts, give up */
995 static int rk_edp_ofdata_to_platdata(struct udevice *dev)
997 struct rk_edp_priv *priv = dev_get_priv(dev);
999 priv->regs = (struct rk3288_edp *)devfdt_get_addr(dev);
1000 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1005 static int rk_edp_remove(struct udevice *dev)
1007 struct rk_edp_priv *priv = dev_get_priv(dev);
1008 struct rk3288_edp *regs = priv->regs;
1010 setbits_le32(®s->video_ctl_1, VIDEO_MUTE);
1011 clrbits_le32(®s->video_ctl_1, VIDEO_EN);
1012 clrbits_le32(®s->sys_ctl_3, F_HPD | HPD_CTRL);
1013 setbits_le32(®s->func_en_1, SW_FUNC_EN_N);
1018 static int rk_edp_probe(struct udevice *dev)
1020 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1021 struct rk_edp_priv *priv = dev_get_priv(dev);
1022 struct rk3288_edp *regs = priv->regs;
1026 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1029 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1034 int vop_id = uc_plat->source_id;
1035 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1037 ret = clk_get_by_index(dev, 1, &clk);
1039 ret = clk_set_rate(&clk, 0);
1043 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1047 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1049 ret = clk_set_rate(&clk, 192000000);
1053 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1054 __func__, uc_plat->src_dev->name, ret);
1058 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1059 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1061 /* select epd signal from vop0 or vop1 */
1062 rk_setreg(&priv->grf->soc_con6, (vop_id == 1) ? (1 << 5) : (1 << 5));
1064 rockchip_edp_wait_hpd(priv);
1066 rk_edp_init_refclk(regs);
1067 rk_edp_init_interrupt(regs);
1068 rk_edp_enable_sw_function(regs);
1069 ret = rk_edp_init_analog_func(regs);
1072 rk_edp_init_aux(regs);
1077 static const struct dm_display_ops dp_rockchip_ops = {
1078 .read_edid = rk_edp_read_edid,
1079 .enable = rk_edp_enable,
1082 static const struct udevice_id rockchip_dp_ids[] = {
1083 { .compatible = "rockchip,rk3288-edp" },
1087 U_BOOT_DRIVER(dp_rockchip) = {
1088 .name = "edp_rockchip",
1089 .id = UCLASS_DISPLAY,
1090 .of_match = rockchip_dp_ids,
1091 .ops = &dp_rockchip_ops,
1092 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1093 .probe = rk_edp_probe,
1094 .remove = rk_edp_remove,
1095 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),