drivers/video/rockchip/rk3288_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <display.h>
   9 #include <dm.h>
  10 #include <dw_hdmi.h>
  11 #include <edid.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/hardware.h>
  18 #include <asm/arch-rockchip/grf_rk3288.h>
  19 #include <power/regulator.h>
  20 #include "rk_hdmi.h"
  21
  22 static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp,
  23                               const struct display_timing *edid)
  24 {
  25         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  26         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
  27         int vop_id = uc_plat->source_id;
  28         struct rk3288_grf *grf = priv->grf;
  29
  30         /* hdmi source select hdmi controller */
  31         rk_setreg(&grf->soc_con6, 1 << 15);
  32
  33         /* hdmi data from vop id */
  34         rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0);
  35
  36         return dw_hdmi_enable(&priv->hdmi, edid);
  37 }
  38
  39 static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev)
  40 {
  41         struct rk_hdmi_priv *priv = dev_get_priv(dev);
  42         struct dw_hdmi *hdmi = &priv->hdmi;
  43
  44         hdmi->i2c_clk_high = 0x7a;
  45         hdmi->i2c_clk_low = 0x8d;
  46
  47         /*
  48          * TODO(sjg@chromium.org): The above values don't work - these
  49          * ones work better, but generate lots of errors in the data.
  50          */
  51         hdmi->i2c_clk_high = 0x0d;
  52         hdmi->i2c_clk_low = 0x0d;
  53
  54         return rk_hdmi_ofdata_to_platdata(dev);
  55 }
  56
  57 static int rk3288_clk_config(struct udevice *dev)
  58 {
  59         struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
  60         struct clk clk;
  61         int ret;
  62
  63         /*
  64          * Configure the maximum clock to permit whatever resolution the
  65          * monitor wants
  66          */
  67         ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
  68         if (ret >= 0) {
  69                 ret = clk_set_rate(&clk, 384000000);
  70                 clk_free(&clk);
  71         }
  72         if (ret < 0) {
  73                 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
  74                       __func__, uc_plat->src_dev->name, ret);
  75                 return ret;
  76         }
  77
  78         return 0;
  79 }
  80
  81 static const char * const rk3288_regulator_names[] = {
  82         "vcc50_hdmi"
  83 };
  84
  85 static int rk3288_hdmi_probe(struct udevice *dev)
  86 {
  87         /* Enable VOP clock for RK3288 */
  88         rk3288_clk_config(dev);
  89
  90         /* Enable regulators required for HDMI */
  91         rk_hdmi_probe_regulators(dev, rk3288_regulator_names,
  92                                  ARRAY_SIZE(rk3288_regulator_names));
  93
  94         return rk_hdmi_probe(dev);
  95 }
  96
  97 static const struct dm_display_ops rk3288_hdmi_ops = {
  98         .read_edid = rk_hdmi_read_edid,
  99         .enable = rk3288_hdmi_enable,
 100 };
 101
 102 static const struct udevice_id rk3288_hdmi_ids[] = {
 103         { .compatible = "rockchip,rk3288-dw-hdmi" },
 104         { }
 105 };
 106
 107 U_BOOT_DRIVER(rk3288_hdmi_rockchip) = {
 108         .name = "rk3288_hdmi_rockchip",
 109         .id = UCLASS_DISPLAY,
 110         .of_match = rk3288_hdmi_ids,
 111         .ops = &rk3288_hdmi_ops,
 112         .ofdata_to_platdata = rk3288_hdmi_ofdata_to_platdata,
 113         .probe = rk3288_hdmi_probe,
 114         .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
 115 };