drivers/video/raydium-rm68200.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
   4  * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
   5  *            Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
   6  *
   7  * This rm68200 panel driver is inspired from the Linux Kernel driver
   8  * drivers/gpu/drm/panel/panel-raydium-rm68200.c.
   9  */
  10 #include <common.h>
  11 #include <backlight.h>
  12 #include <dm.h>
  13 #include <mipi_dsi.h>
  14 #include <panel.h>
  15 #include <asm/gpio.h>
  16 #include <power/regulator.h>
  17
  18 /*** Manufacturer Command Set ***/
  19 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
  20 #define MCS_CMD1_UCS    0x00 /* User Command Set (UCS = CMD1) */
  21 #define MCS_CMD2_P0     0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
  22 #define MCS_CMD2_P1     0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
  23 #define MCS_CMD2_P2     0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
  24 #define MCS_CMD2_P3     0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
  25
  26 /* CMD2 P0 commands (Display Options and Power) */
  27 #define MCS_STBCTR      0x12 /* TE1 Output Setting Zig-Zag Connection */
  28 #define MCS_SGOPCTR     0x16 /* Source Bias Current */
  29 #define MCS_SDCTR       0x1A /* Source Output Delay Time */
  30 #define MCS_INVCTR      0x1B /* Inversion Type */
  31 #define MCS_EXT_PWR_IC  0x24 /* External PWR IC Control */
  32 #define MCS_SETAVDD     0x27 /* PFM Control for AVDD Output */
  33 #define MCS_SETAVEE     0x29 /* PFM Control for AVEE Output */
  34 #define MCS_BT2CTR      0x2B /* DDVDL Charge Pump Control */
  35 #define MCS_BT3CTR      0x2F /* VGH Charge Pump Control */
  36 #define MCS_BT4CTR      0x34 /* VGL Charge Pump Control */
  37 #define MCS_VCMCTR      0x46 /* VCOM Output Level Control */
  38 #define MCS_SETVGN      0x52 /* VG M/S N Control */
  39 #define MCS_SETVGP      0x54 /* VG M/S P Control */
  40 #define MCS_SW_CTRL     0x5F /* Interface Control for PFM and MIPI */
  41
  42 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
  43 #define GOA_VSTV1               0x00
  44 #define GOA_VSTV2               0x07
  45 #define GOA_VCLK1               0x0E
  46 #define GOA_VCLK2               0x17
  47 #define GOA_VCLK_OPT1           0x20
  48 #define GOA_BICLK1              0x2A
  49 #define GOA_BICLK2              0x37
  50 #define GOA_BICLK3              0x44
  51 #define GOA_BICLK4              0x4F
  52 #define GOA_BICLK_OPT1          0x5B
  53 #define GOA_BICLK_OPT2          0x60
  54 #define MCS_GOA_GPO1            0x6D
  55 #define MCS_GOA_GPO2            0x71
  56 #define MCS_GOA_EQ              0x74
  57 #define MCS_GOA_CLK_GALLON      0x7C
  58 #define MCS_GOA_FS_SEL0         0x7E
  59 #define MCS_GOA_FS_SEL1         0x87
  60 #define MCS_GOA_FS_SEL2         0x91
  61 #define MCS_GOA_FS_SEL3         0x9B
  62 #define MCS_GOA_BS_SEL0         0xAC
  63 #define MCS_GOA_BS_SEL1         0xB5
  64 #define MCS_GOA_BS_SEL2         0xBF
  65 #define MCS_GOA_BS_SEL3         0xC9
  66 #define MCS_GOA_BS_SEL4         0xD3
  67
  68 /* CMD2 P3 commands (Gamma) */
  69 #define MCS_GAMMA_VP            0x60 /* Gamma VP1~VP16 */
  70 #define MCS_GAMMA_VN            0x70 /* Gamma VN1~VN16 */
  71
  72 struct rm68200_panel_priv {
  73         struct udevice *reg;
  74         struct udevice *backlight;
  75         struct gpio_desc reset;
  76         unsigned int lanes;
  77         enum mipi_dsi_pixel_format format;
  78         unsigned long mode_flags;
  79 };
  80
  81 static const struct display_timing default_timing = {
  82         .pixelclock.typ         = 54000000,
  83         .hactive.typ            = 720,
  84         .hfront_porch.typ       = 48,
  85         .hback_porch.typ        = 48,
  86         .hsync_len.typ          = 9,
  87         .vactive.typ            = 1280,
  88         .vfront_porch.typ       = 12,
  89         .vback_porch.typ        = 12,
  90         .vsync_len.typ          = 5,
  91 };
  92
  93 static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
  94                                   size_t len)
  95 {
  96         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
  97         struct mipi_dsi_device *device = plat->device;
  98         int err;
  99
 100         err = mipi_dsi_dcs_write_buffer(device, data, len);
 101         if (err < 0)
 102                 dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
 103 }
 104
 105 static void rm68200_dcs_write_cmd(struct udevice *dev, u8 cmd, u8 value)
 106 {
 107         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 108         struct mipi_dsi_device *device = plat->device;
 109         int err;
 110
 111         err = mipi_dsi_dcs_write(device, cmd, &value, 1);
 112         if (err < 0)
 113                 dev_err(dev, "MIPI DSI DCS write failed: %d\n", err);
 114 }
 115
 116 #define dcs_write_seq(ctx, seq...)                              \
 117 ({                                                              \
 118         static const u8 d[] = { seq };                          \
 119                                                                 \
 120         rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));           \
 121 })
 122
 123 /*
 124  * This panel is not able to auto-increment all cmd addresses so for some of
 125  * them, we need to send them one by one...
 126  */
 127 #define dcs_write_cmd_seq(ctx, cmd, seq...)                     \
 128 ({                                                              \
 129         static const u8 d[] = { seq };                          \
 130         unsigned int i;                                         \
 131                                                                 \
 132         for (i = 0; i < ARRAY_SIZE(d) ; i++)                    \
 133                 rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);      \
 134 })
 135
 136 static void rm68200_init_sequence(struct udevice *dev)
 137 {
 138         /* Enter CMD2 with page 0 */
 139         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P0);
 140         dcs_write_cmd_seq(dev, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
 141         dcs_write_seq(dev, MCS_BT2CTR, 0xE5);
 142         dcs_write_seq(dev, MCS_SETAVDD, 0x0A);
 143         dcs_write_seq(dev, MCS_SETAVEE, 0x0A);
 144         dcs_write_seq(dev, MCS_SGOPCTR, 0x52);
 145         dcs_write_seq(dev, MCS_BT3CTR, 0x53);
 146         dcs_write_seq(dev, MCS_BT4CTR, 0x5A);
 147         dcs_write_seq(dev, MCS_INVCTR, 0x00);
 148         dcs_write_seq(dev, MCS_STBCTR, 0x0A);
 149         dcs_write_seq(dev, MCS_SDCTR, 0x06);
 150         dcs_write_seq(dev, MCS_VCMCTR, 0x56);
 151         dcs_write_seq(dev, MCS_SETVGN, 0xA0, 0x00);
 152         dcs_write_seq(dev, MCS_SETVGP, 0xA0, 0x00);
 153         dcs_write_seq(dev, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 154
 155         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 156         dcs_write_seq(dev, GOA_VSTV1, 0x05);
 157         dcs_write_seq(dev, 0x02, 0x0B);
 158         dcs_write_seq(dev, 0x03, 0x0F);
 159         dcs_write_seq(dev, 0x04, 0x7D, 0x00, 0x50);
 160         dcs_write_cmd_seq(dev, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 161                           0x50);
 162         dcs_write_cmd_seq(dev, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 163                           0x00, 0x85, 0x08);
 164         dcs_write_cmd_seq(dev, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 165                           0x00, 0x85, 0x08);
 166         dcs_write_seq(dev, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 167                       0x00, 0x00, 0x00, 0x00);
 168         dcs_write_cmd_seq(dev, GOA_BICLK1, 0x07, 0x08);
 169         dcs_write_seq(dev, 0x2D, 0x01);
 170         dcs_write_seq(dev, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
 171                       0x00);
 172         dcs_write_cmd_seq(dev, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
 173         dcs_write_seq(dev, 0x3D, 0x40);
 174         dcs_write_seq(dev, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
 175         dcs_write_seq(dev, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 176                       0x00, 0x00, 0x00, 0x00, 0x00);
 177         dcs_write_seq(dev, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 178                       0x00, 0x00);
 179         dcs_write_seq(dev, 0x58, 0x00, 0x00, 0x00);
 180         dcs_write_seq(dev, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
 181         dcs_write_seq(dev, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 182                       0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
 183         dcs_write_seq(dev, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
 184         dcs_write_seq(dev, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
 185         dcs_write_seq(dev, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 186                       0x00, 0x00);
 187         dcs_write_seq(dev, MCS_GOA_CLK_GALLON, 0x00, 0x00);
 188         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 189                           0x16, 0x12, 0x08, 0x3F);
 190         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 191                           0x0A, 0x0E, 0x3F, 0x3F, 0x00);
 192         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 193                           0x05, 0x01, 0x3F, 0x3F, 0x0F);
 194         dcs_write_cmd_seq(dev, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 195                           0x3F);
 196         dcs_write_cmd_seq(dev, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
 197         dcs_write_cmd_seq(dev, 0xA9, 0x07, 0x03, 0x3F);
 198         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 199                           0x15, 0x11, 0x0F, 0x3F);
 200         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 201                           0x0D, 0x09, 0x3F, 0x3F, 0x07);
 202         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 203                           0x02, 0x06, 0x3F, 0x3F, 0x08);
 204         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 205                           0x3F, 0x3F, 0x0E, 0x10, 0x14);
 206         dcs_write_cmd_seq(dev, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
 207         dcs_write_seq(dev, 0xDC, 0x02);
 208         dcs_write_seq(dev, 0xDE, 0x12);
 209
 210         dcs_write_seq(dev, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
 211         dcs_write_seq(dev, 0x01, 0x75);
 212
 213         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD2_P3);
 214         dcs_write_cmd_seq(dev, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 215                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 216                           0x12, 0x0C, 0x00);
 217         dcs_write_cmd_seq(dev, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 218                           0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 219                           0x12, 0x0C, 0x00);
 220
 221         /* Exit CMD2 */
 222         dcs_write_seq(dev, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 223 }
 224
 225 static int rm68200_panel_enable_backlight(struct udevice *dev)
 226 {
 227         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 228         struct mipi_dsi_device *device = plat->device;
 229         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 230         int ret;
 231
 232         ret = mipi_dsi_attach(device);
 233         if (ret < 0)
 234                 return ret;
 235
 236         rm68200_init_sequence(dev);
 237
 238         ret = mipi_dsi_dcs_exit_sleep_mode(device);
 239         if (ret)
 240                 return ret;
 241
 242         mdelay(125);
 243
 244         ret = mipi_dsi_dcs_set_display_on(device);
 245         if (ret)
 246                 return ret;
 247
 248         mdelay(20);
 249
 250         ret = backlight_enable(priv->backlight);
 251         if (ret)
 252                 return ret;
 253
 254         return 0;
 255 }
 256
 257 static int rm68200_panel_get_display_timing(struct udevice *dev,
 258                                             struct display_timing *timings)
 259 {
 260         struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
 261         struct mipi_dsi_device *device = plat->device;
 262         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 263
 264         memcpy(timings, &default_timing, sizeof(*timings));
 265
 266         /* fill characteristics of DSI data link */
 267         device->lanes = priv->lanes;
 268         device->format = priv->format;
 269         device->mode_flags = priv->mode_flags;
 270
 271         return 0;
 272 }
 273
 274 static int rm68200_panel_ofdata_to_platdata(struct udevice *dev)
 275 {
 276         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 277         int ret;
 278
 279         if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
 280                 ret =  device_get_supply_regulator(dev, "power-supply",
 281                                                    &priv->reg);
 282                 if (ret && ret != -ENOENT) {
 283                         dev_err(dev, "Warning: cannot get power supply\n");
 284                         return ret;
 285                 }
 286         }
 287
 288         ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
 289                                    GPIOD_IS_OUT);
 290         if (ret) {
 291                 dev_err(dev, "Warning: cannot get reset GPIO\n");
 292                 if (ret != -ENOENT)
 293                         return ret;
 294         }
 295
 296         ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
 297                                            "backlight", &priv->backlight);
 298         if (ret) {
 299                 dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
 300                 return ret;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int rm68200_panel_probe(struct udevice *dev)
 307 {
 308         struct rm68200_panel_priv *priv = dev_get_priv(dev);
 309         int ret;
 310
 311         if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
 312                 ret = regulator_set_enable(priv->reg, true);
 313                 if (ret)
 314                         return ret;
 315         }
 316
 317         /* reset panel */
 318         dm_gpio_set_value(&priv->reset, true);
 319         mdelay(1);
 320         dm_gpio_set_value(&priv->reset, false);
 321         mdelay(10);
 322
 323         priv->lanes = 2;
 324         priv->format = MIPI_DSI_FMT_RGB888;
 325         priv->mode_flags = MIPI_DSI_MODE_VIDEO |
 326                            MIPI_DSI_MODE_VIDEO_BURST |
 327                            MIPI_DSI_MODE_LPM;
 328
 329         return 0;
 330 }
 331
 332 static const struct panel_ops rm68200_panel_ops = {
 333         .enable_backlight = rm68200_panel_enable_backlight,
 334         .get_display_timing = rm68200_panel_get_display_timing,
 335 };
 336
 337 static const struct udevice_id rm68200_panel_ids[] = {
 338         { .compatible = "raydium,rm68200" },
 339         { }
 340 };
 341
 342 U_BOOT_DRIVER(rm68200_panel) = {
 343         .name                     = "rm68200_panel",
 344         .id                       = UCLASS_PANEL,
 345         .of_match                 = rm68200_panel_ids,
 346         .ops                      = &rm68200_panel_ops,
 347         .ofdata_to_platdata       = rm68200_panel_ofdata_to_platdata,
 348         .probe                    = rm68200_panel_probe,
 349         .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
 350         .priv_auto_alloc_size   = sizeof(struct rm68200_panel_priv),
 351 };