1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 STMicroelectronics - All Rights Reserved
4 * Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
5 * Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
7 * This otm8009a panel driver is inspired from the Linux Kernel driver
8 * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
11 #include <backlight.h>
16 #include <power/regulator.h>
18 #define OTM8009A_BACKLIGHT_DEFAULT 240
19 #define OTM8009A_BACKLIGHT_MAX 255
21 /* Manufacturer Command Set */
22 #define MCS_ADRSFT 0x0000 /* Address Shift Function */
23 #define MCS_PANSET 0xB3A6 /* Panel Type Setting */
24 #define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
25 #define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
26 #define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
27 #define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
28 #define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
29 #define MCS_NO_DOC1 0xC48A /* Command not documented */
30 #define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
31 #define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
32 #define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
33 #define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
34 #define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
35 #define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
36 #define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
37 #define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
38 #define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
39 #define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
40 #define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
41 #define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
42 #define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
43 #define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
44 #define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
45 #define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
46 #define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
47 #define MCS_GOAVST 0xCE80 /* GOA VST Setting */
48 #define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
49 #define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
50 #define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
51 #define MCS_NO_DOC2 0xCFD0 /* Command not documented */
52 #define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
53 #define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
54 #define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
55 #define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
56 #define MCS_NO_DOC3 0xF5B6 /* Command not documented */
57 #define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
58 #define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
60 struct otm8009a_panel_priv {
62 struct gpio_desc reset;
64 enum mipi_dsi_pixel_format format;
65 unsigned long mode_flags;
68 static const struct display_timing default_timing = {
69 .pixelclock.typ = 29700000,
71 .hfront_porch.typ = 98,
72 .hback_porch.typ = 98,
75 .vfront_porch.typ = 15,
76 .vback_porch.typ = 14,
80 static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
83 struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
84 struct mipi_dsi_device *device = plat->device;
86 if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
87 dev_err(dev, "mipi dsi dcs write buffer failed\n");
90 static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
93 struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
94 struct mipi_dsi_device *device = plat->device;
96 /* data will be sent in dsi hs mode (ie. no lpm) */
97 device->mode_flags &= ~MIPI_DSI_MODE_LPM;
99 if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
100 dev_err(dev, "mipi dsi dcs write buffer failed\n");
102 /* restore back the dsi lpm mode */
103 device->mode_flags |= MIPI_DSI_MODE_LPM;
106 #define dcs_write_seq(dev, seq...) \
108 static const u8 d[] = { seq }; \
109 otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d)); \
112 #define dcs_write_seq_hs(dev, seq...) \
114 static const u8 d[] = { seq }; \
115 otm8009a_dcs_write_buf_hs(dev, d, ARRAY_SIZE(d)); \
118 #define dcs_write_cmd_at(dev, cmd, seq...) \
120 static const u16 c = cmd; \
121 struct udevice *device = dev; \
122 dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF); \
123 dcs_write_seq(device, (c) >> 8, seq); \
126 static int otm8009a_init_sequence(struct udevice *dev)
128 struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
129 struct mipi_dsi_device *device = plat->device;
133 dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
135 /* Enter Orise Command2 */
136 dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09);
138 dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30);
141 dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40);
144 dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9);
145 dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34);
146 dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50);
147 dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E);
148 dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */
149 dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01);
150 dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34);
151 dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33);
152 dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79);
153 dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B);
154 dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83);
155 dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83);
156 dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E);
157 dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01);
159 dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
160 dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
161 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
162 dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
163 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
164 dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
165 0x01, 0x02, 0x00, 0x00);
167 dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00);
169 dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
170 dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
172 dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
174 dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
175 dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
177 dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
179 dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
180 dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
181 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
183 dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
184 0x00, 0x00, 0x00, 0x00);
185 dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
186 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
187 dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
189 dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
190 0x00, 0x00, 0x00, 0x00);
191 dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
193 dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
196 dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66);
198 dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06);
200 dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
201 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
203 dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
204 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
208 dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
210 ret = mipi_dsi_dcs_nop(device);
214 ret = mipi_dsi_dcs_exit_sleep_mode(device);
218 /* Wait for sleep out exit */
221 /* Default portrait 480x800 rgb24 */
222 dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
224 ret = mipi_dsi_dcs_set_column_address(device, 0,
225 default_timing.hactive.typ - 1);
229 ret = mipi_dsi_dcs_set_page_address(device, 0,
230 default_timing.vactive.typ - 1);
234 /* See otm8009a driver documentation for pixel format descriptions */
235 ret = mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT |
236 MIPI_DCS_PIXEL_FMT_24BIT << 4);
240 /* Disable CABC feature */
241 dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
243 ret = mipi_dsi_dcs_set_display_on(device);
247 ret = mipi_dsi_dcs_nop(device);
251 /* Send Command GRAM memory write (no parameters) */
252 dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START);
257 static int otm8009a_panel_enable_backlight(struct udevice *dev)
259 struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
260 struct mipi_dsi_device *device = plat->device;
263 ret = mipi_dsi_attach(device);
267 ret = otm8009a_init_sequence(dev);
272 * Power on the backlight with the requested brightness
273 * Note We can not use mipi_dsi_dcs_set_display_brightness()
274 * as otm8009a driver support only 8-bit brightness (1 param).
276 dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
277 OTM8009A_BACKLIGHT_DEFAULT);
279 /* Update Brightness Control & Backlight */
280 dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
282 /* Update Brightness Control & Backlight */
283 dcs_write_seq_hs(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY);
285 /* Need to wait a few time before sending the first image */
291 static int otm8009a_panel_get_display_timing(struct udevice *dev,
292 struct display_timing *timings)
294 struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
295 struct mipi_dsi_device *device = plat->device;
296 struct otm8009a_panel_priv *priv = dev_get_priv(dev);
298 memcpy(timings, &default_timing, sizeof(*timings));
300 /* fill characteristics of DSI data link */
301 device->lanes = priv->lanes;
302 device->format = priv->format;
303 device->mode_flags = priv->mode_flags;
308 static int otm8009a_panel_ofdata_to_platdata(struct udevice *dev)
310 struct otm8009a_panel_priv *priv = dev_get_priv(dev);
313 if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
314 ret = device_get_supply_regulator(dev, "power-supply",
316 if (ret && ret != -ENOENT) {
317 dev_err(dev, "Warning: cannot get power supply\n");
322 ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
325 dev_err(dev, "warning: cannot get reset GPIO\n");
333 static int otm8009a_panel_probe(struct udevice *dev)
335 struct otm8009a_panel_priv *priv = dev_get_priv(dev);
338 if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
339 dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
340 ret = regulator_set_enable(priv->reg, true);
346 dm_gpio_set_value(&priv->reset, true);
347 mdelay(1); /* >50us */
348 dm_gpio_set_value(&priv->reset, false);
349 mdelay(10); /* >5ms */
352 priv->format = MIPI_DSI_FMT_RGB888;
353 priv->mode_flags = MIPI_DSI_MODE_VIDEO |
354 MIPI_DSI_MODE_VIDEO_BURST |
360 static const struct panel_ops otm8009a_panel_ops = {
361 .enable_backlight = otm8009a_panel_enable_backlight,
362 .get_display_timing = otm8009a_panel_get_display_timing,
365 static const struct udevice_id otm8009a_panel_ids[] = {
366 { .compatible = "orisetech,otm8009a" },
370 U_BOOT_DRIVER(otm8009a_panel) = {
371 .name = "otm8009a_panel",
373 .of_match = otm8009a_panel_ids,
374 .ops = &otm8009a_panel_ops,
375 .ofdata_to_platdata = otm8009a_panel_ofdata_to_platdata,
376 .probe = otm8009a_panel_probe,
377 .platdata_auto_alloc_size = sizeof(struct mipi_dsi_panel_plat),
378 .priv_auto_alloc_size = sizeof(struct otm8009a_panel_priv),