1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX23/i.MX28 LCDIF driver
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
9 #include <linux/errno.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/dma.h>
20 #include "videomodes.h"
22 #define PS2KHZ(ps) (1000000000UL / (ps))
23 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
28 struct mxs_dma_desc desc;
31 * mxsfb_system_setup() - Fine-tune LCDIF configuration
33 * This function is used to adjust the LCDIF configuration. This is usually
34 * needed when driving the controller in System-Mode to operate an 8080 or
35 * 6800 connected SmartLCD.
37 __weak void mxsfb_system_setup(void)
44 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
45 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
47 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
49 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
50 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
53 static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
55 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
56 uint32_t word_len = 0, bus_width = 0;
57 uint8_t valid_data = 0;
59 /* Kick in the LCDIF clock */
60 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
62 /* Restart the LCDIF block */
63 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
67 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
68 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
72 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
73 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
77 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
78 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
82 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
83 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
88 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
89 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
90 ®s->hw_lcdif_ctrl);
92 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
93 ®s->hw_lcdif_ctrl1);
97 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
98 ®s->hw_lcdif_transfer_count);
100 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
101 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
102 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
103 mode->vsync_len, ®s->hw_lcdif_vdctrl0);
104 writel(mode->upper_margin + mode->lower_margin +
105 mode->vsync_len + mode->yres,
106 ®s->hw_lcdif_vdctrl1);
107 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
108 (mode->left_margin + mode->right_margin +
109 mode->hsync_len + mode->xres),
110 ®s->hw_lcdif_vdctrl2);
111 writel(((mode->left_margin + mode->hsync_len) <<
112 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
113 (mode->upper_margin + mode->vsync_len),
114 ®s->hw_lcdif_vdctrl3);
115 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
116 ®s->hw_lcdif_vdctrl4);
118 writel(fb_addr, ®s->hw_lcdif_cur_buf);
119 writel(fb_addr, ®s->hw_lcdif_next_buf);
121 /* Flush FIFO first */
122 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
124 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
125 /* Sync signals ON */
126 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
130 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
133 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
136 static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
138 /* Start framebuffer */
139 mxs_lcd_init(fb, mode, bpp);
141 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
143 * If the LCD runs in system mode, the LCD refresh has to be triggered
144 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
145 * having to set this bit manually after every single change in the
146 * framebuffer memory, we set up specially crafted circular DMA, which
147 * sets the RUN bit, then waits until it gets cleared and repeats this
148 * infinitelly. This way, we get smooth continuous updates of the LCD.
150 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
152 memset(&desc, 0, sizeof(struct mxs_dma_desc));
153 desc.address = (dma_addr_t)&desc;
154 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
155 MXS_DMA_DESC_WAIT4END |
156 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
157 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
158 desc.cmd.next = (uint32_t)&desc.cmd;
160 /* Execute the DMA chain. */
161 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
167 static int mxs_remove_common(u32 fb)
169 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
170 int timeout = 1000000;
175 writel(fb, ®s->hw_lcdif_cur_buf_reg);
176 writel(fb, ®s->hw_lcdif_next_buf_reg);
177 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
179 if (readl(®s->hw_lcdif_ctrl1_reg) &
180 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
184 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
189 #ifndef CONFIG_DM_VIDEO
191 static GraphicDevice panel;
193 void lcdif_power_down(void)
195 mxs_remove_common(panel.frameAdrs);
198 void *video_hw_init(void)
204 struct ctfb_res_modes mode;
208 /* Suck display configuration from "videomode" variable */
209 penv = env_get("videomode");
211 puts("MXSFB: 'videomode' variable not set!\n");
215 bpp = video_get_params(&mode, penv);
217 /* fill in Graphic device struct */
218 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
220 panel.winSizeX = mode.xres;
221 panel.winSizeY = mode.yres;
222 panel.plnSizeX = mode.xres;
223 panel.plnSizeY = mode.yres;
228 panel.gdfBytesPP = 4;
229 panel.gdfIndex = GDF_32BIT_X888RGB;
232 panel.gdfBytesPP = 2;
233 panel.gdfIndex = GDF_16BIT_565RGB;
236 panel.gdfBytesPP = 1;
237 panel.gdfIndex = GDF__8BIT_INDEX;
240 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
244 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
246 /* Allocate framebuffer */
247 fb = memalign(ARCH_DMA_MINALIGN,
248 roundup(panel.memSize, ARCH_DMA_MINALIGN));
250 printf("MXSFB: Error allocating framebuffer!\n");
254 /* Wipe framebuffer */
255 memset(fb, 0, panel.memSize);
257 panel.frameAdrs = (u32)fb;
259 printf("%s\n", panel.modeIdent);
261 ret = mxs_probe_common(&mode, bpp, (u32)fb);
265 return (void *)&panel;
272 #else /* ifndef CONFIG_DM_VIDEO */
274 static int mxs_of_get_timings(struct udevice *dev,
275 struct display_timing *timings,
282 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
284 dev_err(dev, "required display property isn't provided\n");
288 display_node = ofnode_get_by_phandle(display_phandle);
289 if (!ofnode_valid(display_node)) {
290 dev_err(dev, "failed to find display subnode\n");
294 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
297 "required bits-per-pixel property isn't provided\n");
301 ret = ofnode_decode_display_timing(display_node, 0, timings);
303 dev_err(dev, "failed to get any display timings\n");
310 static int mxs_video_probe(struct udevice *dev)
312 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
313 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
315 struct ctfb_res_modes mode;
316 struct display_timing timings;
318 u32 fb_start, fb_end;
321 debug("%s() plat: base 0x%lx, size 0x%x\n",
322 __func__, plat->base, plat->size);
324 ret = mxs_of_get_timings(dev, &timings, &bpp);
328 mode.xres = timings.hactive.typ;
329 mode.yres = timings.vactive.typ;
330 mode.left_margin = timings.hback_porch.typ;
331 mode.right_margin = timings.hfront_porch.typ;
332 mode.upper_margin = timings.vback_porch.typ;
333 mode.lower_margin = timings.vfront_porch.typ;
334 mode.hsync_len = timings.hsync_len.typ;
335 mode.vsync_len = timings.vsync_len.typ;
336 mode.pixclock = HZ2PS(timings.pixelclock.typ);
338 ret = mxs_probe_common(&mode, bpp, plat->base);
346 uc_priv->bpix = VIDEO_BPP32;
349 uc_priv->bpix = VIDEO_BPP16;
352 uc_priv->bpix = VIDEO_BPP8;
355 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
359 uc_priv->xsize = mode.xres;
360 uc_priv->ysize = mode.yres;
362 /* Enable dcache for the frame buffer */
363 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
364 fb_end = plat->base + plat->size;
365 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
366 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
368 video_set_flush_dcache(dev, true);
373 static int mxs_video_bind(struct udevice *dev)
375 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
376 struct display_timing timings;
381 ret = mxs_of_get_timings(dev, &timings, &bpp);
398 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
402 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
407 static int mxs_video_remove(struct udevice *dev)
409 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
411 mxs_remove_common(plat->base);
416 static const struct udevice_id mxs_video_ids[] = {
417 { .compatible = "fsl,imx23-lcdif" },
418 { .compatible = "fsl,imx28-lcdif" },
419 { .compatible = "fsl,imx7ulp-lcdif" },
423 U_BOOT_DRIVER(mxs_video) = {
426 .of_match = mxs_video_ids,
427 .bind = mxs_video_bind,
428 .probe = mxs_video_probe,
429 .remove = mxs_video_remove,
430 .flags = DM_FLAG_PRE_RELOC,
432 #endif /* ifndef CONFIG_DM_VIDEO */