1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX23/i.MX28 LCDIF driver
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
11 #include <dm/device_compat.h>
12 #include <linux/errno.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/mach-imx/dma.h>
23 #include "videomodes.h"
25 #define PS2KHZ(ps) (1000000000UL / (ps))
26 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
31 struct mxs_dma_desc desc;
34 * mxsfb_system_setup() - Fine-tune LCDIF configuration
36 * This function is used to adjust the LCDIF configuration. This is usually
37 * needed when driving the controller in System-Mode to operate an 8080 or
38 * 6800 connected SmartLCD.
40 __weak void mxsfb_system_setup(void)
47 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
48 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
50 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
52 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
53 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
56 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
57 struct ctfb_res_modes *mode, int bpp)
59 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
60 uint32_t word_len = 0, bus_width = 0;
61 uint8_t valid_data = 0;
63 #if CONFIG_IS_ENABLED(CLK)
67 ret = clk_get_by_name(dev, "per", &per_clk);
69 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
73 ret = clk_set_rate(&per_clk, PS2KHZ(mode->pixclock) * 1000);
75 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
79 /* Kick in the LCDIF clock */
80 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
83 /* Restart the LCDIF block */
84 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
88 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
89 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
93 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
94 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
98 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
99 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
103 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
104 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
109 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
110 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
111 ®s->hw_lcdif_ctrl);
113 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
114 ®s->hw_lcdif_ctrl1);
116 mxsfb_system_setup();
118 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
119 ®s->hw_lcdif_transfer_count);
121 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
122 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
123 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
124 mode->vsync_len, ®s->hw_lcdif_vdctrl0);
125 writel(mode->upper_margin + mode->lower_margin +
126 mode->vsync_len + mode->yres,
127 ®s->hw_lcdif_vdctrl1);
128 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
129 (mode->left_margin + mode->right_margin +
130 mode->hsync_len + mode->xres),
131 ®s->hw_lcdif_vdctrl2);
132 writel(((mode->left_margin + mode->hsync_len) <<
133 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
134 (mode->upper_margin + mode->vsync_len),
135 ®s->hw_lcdif_vdctrl3);
136 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
137 ®s->hw_lcdif_vdctrl4);
139 writel(fb_addr, ®s->hw_lcdif_cur_buf);
140 writel(fb_addr, ®s->hw_lcdif_next_buf);
142 /* Flush FIFO first */
143 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
145 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
146 /* Sync signals ON */
147 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
151 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
154 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
157 static int mxs_probe_common(struct udevice *dev, struct ctfb_res_modes *mode,
160 /* Start framebuffer */
161 mxs_lcd_init(dev, fb, mode, bpp);
163 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
165 * If the LCD runs in system mode, the LCD refresh has to be triggered
166 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
167 * having to set this bit manually after every single change in the
168 * framebuffer memory, we set up specially crafted circular DMA, which
169 * sets the RUN bit, then waits until it gets cleared and repeats this
170 * infinitelly. This way, we get smooth continuous updates of the LCD.
172 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
174 memset(&desc, 0, sizeof(struct mxs_dma_desc));
175 desc.address = (dma_addr_t)&desc;
176 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
177 MXS_DMA_DESC_WAIT4END |
178 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
179 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
180 desc.cmd.next = (uint32_t)&desc.cmd;
182 /* Execute the DMA chain. */
183 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
189 static int mxs_remove_common(u32 fb)
191 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
192 int timeout = 1000000;
197 writel(fb, ®s->hw_lcdif_cur_buf_reg);
198 writel(fb, ®s->hw_lcdif_next_buf_reg);
199 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
201 if (readl(®s->hw_lcdif_ctrl1_reg) &
202 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
206 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
211 #ifndef CONFIG_DM_VIDEO
213 static GraphicDevice panel;
215 void lcdif_power_down(void)
217 mxs_remove_common(panel.frameAdrs);
220 void *video_hw_init(void)
226 struct ctfb_res_modes mode;
230 /* Suck display configuration from "videomode" variable */
231 penv = env_get("videomode");
233 puts("MXSFB: 'videomode' variable not set!\n");
237 bpp = video_get_params(&mode, penv);
239 /* fill in Graphic device struct */
240 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
242 panel.winSizeX = mode.xres;
243 panel.winSizeY = mode.yres;
244 panel.plnSizeX = mode.xres;
245 panel.plnSizeY = mode.yres;
250 panel.gdfBytesPP = 4;
251 panel.gdfIndex = GDF_32BIT_X888RGB;
254 panel.gdfBytesPP = 2;
255 panel.gdfIndex = GDF_16BIT_565RGB;
258 panel.gdfBytesPP = 1;
259 panel.gdfIndex = GDF__8BIT_INDEX;
262 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
266 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
268 /* Allocate framebuffer */
269 fb = memalign(ARCH_DMA_MINALIGN,
270 roundup(panel.memSize, ARCH_DMA_MINALIGN));
272 printf("MXSFB: Error allocating framebuffer!\n");
276 /* Wipe framebuffer */
277 memset(fb, 0, panel.memSize);
279 panel.frameAdrs = (u32)fb;
281 printf("%s\n", panel.modeIdent);
283 ret = mxs_probe_common(NULL, &mode, bpp, (u32)fb);
287 return (void *)&panel;
294 #else /* ifndef CONFIG_DM_VIDEO */
296 static int mxs_of_get_timings(struct udevice *dev,
297 struct display_timing *timings,
304 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
306 dev_err(dev, "required display property isn't provided\n");
310 display_node = ofnode_get_by_phandle(display_phandle);
311 if (!ofnode_valid(display_node)) {
312 dev_err(dev, "failed to find display subnode\n");
316 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
319 "required bits-per-pixel property isn't provided\n");
323 ret = ofnode_decode_display_timing(display_node, 0, timings);
325 dev_err(dev, "failed to get any display timings\n");
332 static int mxs_video_probe(struct udevice *dev)
334 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
335 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
337 struct ctfb_res_modes mode;
338 struct display_timing timings;
340 u32 fb_start, fb_end;
343 debug("%s() plat: base 0x%lx, size 0x%x\n",
344 __func__, plat->base, plat->size);
346 ret = mxs_of_get_timings(dev, &timings, &bpp);
350 mode.xres = timings.hactive.typ;
351 mode.yres = timings.vactive.typ;
352 mode.left_margin = timings.hback_porch.typ;
353 mode.right_margin = timings.hfront_porch.typ;
354 mode.upper_margin = timings.vback_porch.typ;
355 mode.lower_margin = timings.vfront_porch.typ;
356 mode.hsync_len = timings.hsync_len.typ;
357 mode.vsync_len = timings.vsync_len.typ;
358 mode.pixclock = HZ2PS(timings.pixelclock.typ);
360 ret = mxs_probe_common(dev, &mode, bpp, plat->base);
368 uc_priv->bpix = VIDEO_BPP32;
371 uc_priv->bpix = VIDEO_BPP16;
374 uc_priv->bpix = VIDEO_BPP8;
377 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
381 uc_priv->xsize = mode.xres;
382 uc_priv->ysize = mode.yres;
384 /* Enable dcache for the frame buffer */
385 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
386 fb_end = plat->base + plat->size;
387 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
388 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
390 video_set_flush_dcache(dev, true);
391 gd->fb_base = plat->base;
396 static int mxs_video_bind(struct udevice *dev)
398 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
399 struct display_timing timings;
404 ret = mxs_of_get_timings(dev, &timings, &bpp);
421 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
425 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
430 static int mxs_video_remove(struct udevice *dev)
432 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
434 mxs_remove_common(plat->base);
439 static const struct udevice_id mxs_video_ids[] = {
440 { .compatible = "fsl,imx23-lcdif" },
441 { .compatible = "fsl,imx28-lcdif" },
442 { .compatible = "fsl,imx7ulp-lcdif" },
443 { .compatible = "fsl,imxrt-lcdif" },
447 U_BOOT_DRIVER(mxs_video) = {
450 .of_match = mxs_video_ids,
451 .bind = mxs_video_bind,
452 .probe = mxs_video_probe,
453 .remove = mxs_video_remove,
454 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
456 #endif /* ifndef CONFIG_DM_VIDEO */