1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX23/i.MX28 LCDIF driver
5 * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
10 #include <dm/device_compat.h>
11 #include <linux/errno.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/mach-imx/dma.h>
22 #include "videomodes.h"
24 #define PS2KHZ(ps) (1000000000UL / (ps))
25 #define HZ2PS(hz) (1000000000UL / ((hz) / 1000))
30 struct mxs_dma_desc desc;
33 * mxsfb_system_setup() - Fine-tune LCDIF configuration
35 * This function is used to adjust the LCDIF configuration. This is usually
36 * needed when driving the controller in System-Mode to operate an 8080 or
37 * 6800 connected SmartLCD.
39 __weak void mxsfb_system_setup(void)
46 * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
47 * le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
49 * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
51 * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
52 * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
55 static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp)
57 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
58 uint32_t word_len = 0, bus_width = 0;
59 uint8_t valid_data = 0;
61 /* Kick in the LCDIF clock */
62 mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
64 /* Restart the LCDIF block */
65 mxs_reset_block(®s->hw_lcdif_ctrl_reg);
69 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
70 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
74 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
75 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
79 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
80 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
84 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
85 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
90 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
91 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
92 ®s->hw_lcdif_ctrl);
94 writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
95 ®s->hw_lcdif_ctrl1);
99 writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
100 ®s->hw_lcdif_transfer_count);
102 writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
103 LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
104 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
105 mode->vsync_len, ®s->hw_lcdif_vdctrl0);
106 writel(mode->upper_margin + mode->lower_margin +
107 mode->vsync_len + mode->yres,
108 ®s->hw_lcdif_vdctrl1);
109 writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
110 (mode->left_margin + mode->right_margin +
111 mode->hsync_len + mode->xres),
112 ®s->hw_lcdif_vdctrl2);
113 writel(((mode->left_margin + mode->hsync_len) <<
114 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
115 (mode->upper_margin + mode->vsync_len),
116 ®s->hw_lcdif_vdctrl3);
117 writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
118 ®s->hw_lcdif_vdctrl4);
120 writel(fb_addr, ®s->hw_lcdif_cur_buf);
121 writel(fb_addr, ®s->hw_lcdif_next_buf);
123 /* Flush FIFO first */
124 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_set);
126 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
127 /* Sync signals ON */
128 setbits_le32(®s->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
132 writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
135 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
138 static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, u32 fb)
140 /* Start framebuffer */
141 mxs_lcd_init(fb, mode, bpp);
143 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
145 * If the LCD runs in system mode, the LCD refresh has to be triggered
146 * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
147 * having to set this bit manually after every single change in the
148 * framebuffer memory, we set up specially crafted circular DMA, which
149 * sets the RUN bit, then waits until it gets cleared and repeats this
150 * infinitelly. This way, we get smooth continuous updates of the LCD.
152 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
154 memset(&desc, 0, sizeof(struct mxs_dma_desc));
155 desc.address = (dma_addr_t)&desc;
156 desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
157 MXS_DMA_DESC_WAIT4END |
158 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
159 desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
160 desc.cmd.next = (uint32_t)&desc.cmd;
162 /* Execute the DMA chain. */
163 mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
169 static int mxs_remove_common(u32 fb)
171 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
172 int timeout = 1000000;
177 writel(fb, ®s->hw_lcdif_cur_buf_reg);
178 writel(fb, ®s->hw_lcdif_next_buf_reg);
179 writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, ®s->hw_lcdif_ctrl1_clr);
181 if (readl(®s->hw_lcdif_ctrl1_reg) &
182 LCDIF_CTRL1_VSYNC_EDGE_IRQ)
186 mxs_reset_block((struct mxs_register_32 *)®s->hw_lcdif_ctrl_reg);
191 #ifndef CONFIG_DM_VIDEO
193 static GraphicDevice panel;
195 void lcdif_power_down(void)
197 mxs_remove_common(panel.frameAdrs);
200 void *video_hw_init(void)
206 struct ctfb_res_modes mode;
210 /* Suck display configuration from "videomode" variable */
211 penv = env_get("videomode");
213 puts("MXSFB: 'videomode' variable not set!\n");
217 bpp = video_get_params(&mode, penv);
219 /* fill in Graphic device struct */
220 sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
222 panel.winSizeX = mode.xres;
223 panel.winSizeY = mode.yres;
224 panel.plnSizeX = mode.xres;
225 panel.plnSizeY = mode.yres;
230 panel.gdfBytesPP = 4;
231 panel.gdfIndex = GDF_32BIT_X888RGB;
234 panel.gdfBytesPP = 2;
235 panel.gdfIndex = GDF_16BIT_565RGB;
238 panel.gdfBytesPP = 1;
239 panel.gdfIndex = GDF__8BIT_INDEX;
242 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
246 panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
248 /* Allocate framebuffer */
249 fb = memalign(ARCH_DMA_MINALIGN,
250 roundup(panel.memSize, ARCH_DMA_MINALIGN));
252 printf("MXSFB: Error allocating framebuffer!\n");
256 /* Wipe framebuffer */
257 memset(fb, 0, panel.memSize);
259 panel.frameAdrs = (u32)fb;
261 printf("%s\n", panel.modeIdent);
263 ret = mxs_probe_common(&mode, bpp, (u32)fb);
267 return (void *)&panel;
274 #else /* ifndef CONFIG_DM_VIDEO */
276 static int mxs_of_get_timings(struct udevice *dev,
277 struct display_timing *timings,
284 ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
286 dev_err(dev, "required display property isn't provided\n");
290 display_node = ofnode_get_by_phandle(display_phandle);
291 if (!ofnode_valid(display_node)) {
292 dev_err(dev, "failed to find display subnode\n");
296 ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
299 "required bits-per-pixel property isn't provided\n");
303 ret = ofnode_decode_display_timing(display_node, 0, timings);
305 dev_err(dev, "failed to get any display timings\n");
312 static int mxs_video_probe(struct udevice *dev)
314 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
315 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
317 struct ctfb_res_modes mode;
318 struct display_timing timings;
320 u32 fb_start, fb_end;
323 debug("%s() plat: base 0x%lx, size 0x%x\n",
324 __func__, plat->base, plat->size);
326 ret = mxs_of_get_timings(dev, &timings, &bpp);
330 mode.xres = timings.hactive.typ;
331 mode.yres = timings.vactive.typ;
332 mode.left_margin = timings.hback_porch.typ;
333 mode.right_margin = timings.hfront_porch.typ;
334 mode.upper_margin = timings.vback_porch.typ;
335 mode.lower_margin = timings.vfront_porch.typ;
336 mode.hsync_len = timings.hsync_len.typ;
337 mode.vsync_len = timings.vsync_len.typ;
338 mode.pixclock = HZ2PS(timings.pixelclock.typ);
340 ret = mxs_probe_common(&mode, bpp, plat->base);
348 uc_priv->bpix = VIDEO_BPP32;
351 uc_priv->bpix = VIDEO_BPP16;
354 uc_priv->bpix = VIDEO_BPP8;
357 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
361 uc_priv->xsize = mode.xres;
362 uc_priv->ysize = mode.yres;
364 /* Enable dcache for the frame buffer */
365 fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
366 fb_end = plat->base + plat->size;
367 fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
368 mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
370 video_set_flush_dcache(dev, true);
371 gd->fb_base = plat->base;
376 static int mxs_video_bind(struct udevice *dev)
378 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
379 struct display_timing timings;
384 ret = mxs_of_get_timings(dev, &timings, &bpp);
401 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
405 plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
410 static int mxs_video_remove(struct udevice *dev)
412 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
414 mxs_remove_common(plat->base);
419 static const struct udevice_id mxs_video_ids[] = {
420 { .compatible = "fsl,imx23-lcdif" },
421 { .compatible = "fsl,imx28-lcdif" },
422 { .compatible = "fsl,imx7ulp-lcdif" },
426 U_BOOT_DRIVER(mxs_video) = {
429 .of_match = mxs_video_ids,
430 .bind = mxs_video_bind,
431 .probe = mxs_video_probe,
432 .remove = mxs_video_remove,
433 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
435 #endif /* ifndef CONFIG_DM_VIDEO */