drivers/video/mxsfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX23/i.MX28 LCDIF driver
   4  *
   5  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
   6  */
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <env.h>
  11 #include <dm/device_compat.h>
  12 #include <linux/errno.h>
  13 #include <malloc.h>
  14 #include <video.h>
  15 #include <video_fb.h>
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-imx/dma.h>
  21 #include <asm/io.h>
  22
  23 #include "videomodes.h"
  24
  25 #define PS2KHZ(ps)      (1000000000UL / (ps))
  26 #define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  27
  28 #define BITS_PP         18
  29 #define BYTES_PP        4
  30
  31 struct mxs_dma_desc desc;
  32
  33 /**
  34  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  35  *
  36  * This function is used to adjust the LCDIF configuration. This is usually
  37  * needed when driving the controller in System-Mode to operate an 8080 or
  38  * 6800 connected SmartLCD.
  39  */
  40 __weak void mxsfb_system_setup(void)
  41 {
  42 }
  43
  44 /*
  45  * ARIES M28EVK:
  46  * setenv videomode
  47  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  48  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  49  *
  50  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  51  * setenv videomode
  52  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  53  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  54  */
  55
  56 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  57                          struct display_timing *timings, int bpp)
  58 {
  59         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  60         const enum display_flags flags = timings->flags;
  61         uint32_t word_len = 0, bus_width = 0;
  62         uint8_t valid_data = 0;
  63         uint32_t vdctrl0;
  64
  65 #if CONFIG_IS_ENABLED(CLK)
  66         struct clk per_clk;
  67         int ret;
  68
  69         ret = clk_get_by_name(dev, "per", &per_clk);
  70         if (ret) {
  71                 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  72                 return;
  73         }
  74
  75         ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  76         if (ret < 0) {
  77                 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  78                 return;
  79         }
  80
  81         ret = clk_enable(&per_clk);
  82         if (ret < 0) {
  83                 dev_err(dev, "Failed to enable mxs clk: %d\n", ret);
  84                 return;
  85         }
  86 #else
  87         /* Kick in the LCDIF clock */
  88         mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  89 #endif
  90
  91         /* Restart the LCDIF block */
  92         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  93
  94         switch (bpp) {
  95         case 24:
  96                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  97                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  98                 valid_data = 0x7;
  99                 break;
 100         case 18:
 101                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
 102                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
 103                 valid_data = 0x7;
 104                 break;
 105         case 16:
 106                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 107                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 108                 valid_data = 0xf;
 109                 break;
 110         case 8:
 111                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 112                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 113                 valid_data = 0xf;
 114                 break;
 115         }
 116
 117         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 118                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 119                 &regs->hw_lcdif_ctrl);
 120
 121         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 122                 &regs->hw_lcdif_ctrl1);
 123
 124         mxsfb_system_setup();
 125
 126         writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 127                 timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 128
 129         vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 130                   LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 131                   LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 132                   timings->vsync_len.typ;
 133
 134         if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
 135                 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 136         if(flags & DISPLAY_FLAGS_VSYNC_HIGH)
 137                 vdctrl0 |= LCDIF_VDCTRL0_VSYNC_POL;
 138         if(flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 139                 vdctrl0 |= LCDIF_VDCTRL0_DOTCLK_POL;
 140         if(flags & DISPLAY_FLAGS_DE_HIGH)
 141                 vdctrl0 |= LCDIF_VDCTRL0_ENABLE_POL;
 142
 143         writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 144         writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 145                 timings->vsync_len.typ + timings->vactive.typ,
 146                 &regs->hw_lcdif_vdctrl1);
 147         writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 148                 (timings->hback_porch.typ + timings->hfront_porch.typ +
 149                 timings->hsync_len.typ + timings->hactive.typ),
 150                 &regs->hw_lcdif_vdctrl2);
 151         writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
 152                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 153                 (timings->vback_porch.typ + timings->vsync_len.typ),
 154                 &regs->hw_lcdif_vdctrl3);
 155         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
 156                 &regs->hw_lcdif_vdctrl4);
 157
 158         writel(fb_addr, &regs->hw_lcdif_cur_buf);
 159         writel(fb_addr, &regs->hw_lcdif_next_buf);
 160
 161         /* Flush FIFO first */
 162         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 163
 164 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 165         /* Sync signals ON */
 166         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 167 #endif
 168
 169         /* FIFO cleared */
 170         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 171
 172         /* RUN! */
 173         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 174 }
 175
 176 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 177                             int bpp, u32 fb)
 178 {
 179         /* Start framebuffer */
 180         mxs_lcd_init(dev, fb, timings, bpp);
 181
 182 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 183         /*
 184          * If the LCD runs in system mode, the LCD refresh has to be triggered
 185          * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 186          * having to set this bit manually after every single change in the
 187          * framebuffer memory, we set up specially crafted circular DMA, which
 188          * sets the RUN bit, then waits until it gets cleared and repeats this
 189          * infinitelly. This way, we get smooth continuous updates of the LCD.
 190          */
 191         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 192
 193         memset(&desc, 0, sizeof(struct mxs_dma_desc));
 194         desc.address = (dma_addr_t)&desc;
 195         desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 196                         MXS_DMA_DESC_WAIT4END |
 197                         (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 198         desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 199         desc.cmd.next = (uint32_t)&desc.cmd;
 200
 201         /* Execute the DMA chain. */
 202         mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 203 #endif
 204
 205         return 0;
 206 }
 207
 208 static int mxs_remove_common(u32 fb)
 209 {
 210         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 211         int timeout = 1000000;
 212
 213         if (!fb)
 214                 return -EINVAL;
 215
 216         writel(fb, &regs->hw_lcdif_cur_buf_reg);
 217         writel(fb, &regs->hw_lcdif_next_buf_reg);
 218         writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 219         while (--timeout) {
 220                 if (readl(&regs->hw_lcdif_ctrl1_reg) &
 221                     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 222                         break;
 223                 udelay(1);
 224         }
 225         mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 226
 227         return 0;
 228 }
 229
 230 #ifndef CONFIG_DM_VIDEO
 231
 232 static GraphicDevice panel;
 233
 234 void lcdif_power_down(void)
 235 {
 236         mxs_remove_common(panel.frameAdrs);
 237 }
 238
 239 void *video_hw_init(void)
 240 {
 241         int bpp = -1;
 242         int ret = 0;
 243         char *penv;
 244         void *fb = NULL;
 245         struct ctfb_res_modes mode;
 246         struct display_timing timings;
 247
 248         puts("Video: ");
 249
 250         /* Suck display configuration from "videomode" variable */
 251         penv = env_get("videomode");
 252         if (!penv) {
 253                 puts("MXSFB: 'videomode' variable not set!\n");
 254                 return NULL;
 255         }
 256
 257         bpp = video_get_params(&mode, penv);
 258
 259         /* fill in Graphic device struct */
 260         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 261
 262         panel.winSizeX = mode.xres;
 263         panel.winSizeY = mode.yres;
 264         panel.plnSizeX = mode.xres;
 265         panel.plnSizeY = mode.yres;
 266
 267         switch (bpp) {
 268         case 24:
 269         case 18:
 270                 panel.gdfBytesPP = 4;
 271                 panel.gdfIndex = GDF_32BIT_X888RGB;
 272                 break;
 273         case 16:
 274                 panel.gdfBytesPP = 2;
 275                 panel.gdfIndex = GDF_16BIT_565RGB;
 276                 break;
 277         case 8:
 278                 panel.gdfBytesPP = 1;
 279                 panel.gdfIndex = GDF__8BIT_INDEX;
 280                 break;
 281         default:
 282                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 283                 return NULL;
 284         }
 285
 286         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 287
 288         /* Allocate framebuffer */
 289         fb = memalign(ARCH_DMA_MINALIGN,
 290                       roundup(panel.memSize, ARCH_DMA_MINALIGN));
 291         if (!fb) {
 292                 printf("MXSFB: Error allocating framebuffer!\n");
 293                 return NULL;
 294         }
 295
 296         /* Wipe framebuffer */
 297         memset(fb, 0, panel.memSize);
 298
 299         panel.frameAdrs = (u32)fb;
 300
 301         printf("%s\n", panel.modeIdent);
 302
 303         video_ctfb_mode_to_display_timing(&mode, &timings);
 304
 305         ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
 306         if (ret)
 307                 goto dealloc_fb;
 308
 309         return (void *)&panel;
 310
 311 dealloc_fb:
 312         free(fb);
 313
 314         return NULL;
 315 }
 316 #else /* ifndef CONFIG_DM_VIDEO */
 317
 318 static int mxs_of_get_timings(struct udevice *dev,
 319                               struct display_timing *timings,
 320                               u32 *bpp)
 321 {
 322         int ret = 0;
 323         u32 display_phandle;
 324         ofnode display_node;
 325
 326         ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 327         if (ret) {
 328                 dev_err(dev, "required display property isn't provided\n");
 329                 return -EINVAL;
 330         }
 331
 332         display_node = ofnode_get_by_phandle(display_phandle);
 333         if (!ofnode_valid(display_node)) {
 334                 dev_err(dev, "failed to find display subnode\n");
 335                 return -EINVAL;
 336         }
 337
 338         ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 339         if (ret) {
 340                 dev_err(dev,
 341                         "required bits-per-pixel property isn't provided\n");
 342                 return -EINVAL;
 343         }
 344
 345         ret = ofnode_decode_display_timing(display_node, 0, timings);
 346         if (ret) {
 347                 dev_err(dev, "failed to get any display timings\n");
 348                 return -EINVAL;
 349         }
 350
 351         return ret;
 352 }
 353
 354 static int mxs_video_probe(struct udevice *dev)
 355 {
 356         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 357         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 358
 359         struct display_timing timings;
 360         u32 bpp = 0;
 361         u32 fb_start, fb_end;
 362         int ret;
 363
 364         debug("%s() plat: base 0x%lx, size 0x%x\n",
 365                __func__, plat->base, plat->size);
 366
 367         ret = mxs_of_get_timings(dev, &timings, &bpp);
 368         if (ret)
 369                 return ret;
 370
 371         ret = mxs_probe_common(dev, &timings, bpp, plat->base);
 372         if (ret)
 373                 return ret;
 374
 375         switch (bpp) {
 376         case 32:
 377         case 24:
 378         case 18:
 379                 uc_priv->bpix = VIDEO_BPP32;
 380                 break;
 381         case 16:
 382                 uc_priv->bpix = VIDEO_BPP16;
 383                 break;
 384         case 8:
 385                 uc_priv->bpix = VIDEO_BPP8;
 386                 break;
 387         default:
 388                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 389                 return -EINVAL;
 390         }
 391
 392         uc_priv->xsize = timings.hactive.typ;
 393         uc_priv->ysize = timings.vactive.typ;
 394
 395         /* Enable dcache for the frame buffer */
 396         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 397         fb_end = plat->base + plat->size;
 398         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 399         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 400                                         DCACHE_WRITEBACK);
 401         video_set_flush_dcache(dev, true);
 402         gd->fb_base = plat->base;
 403
 404         return ret;
 405 }
 406
 407 static int mxs_video_bind(struct udevice *dev)
 408 {
 409         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 410         struct display_timing timings;
 411         u32 bpp = 0;
 412         u32 bytes_pp = 0;
 413         int ret;
 414
 415         ret = mxs_of_get_timings(dev, &timings, &bpp);
 416         if (ret)
 417                 return ret;
 418
 419         switch (bpp) {
 420         case 32:
 421         case 24:
 422         case 18:
 423                 bytes_pp = 4;
 424                 break;
 425         case 16:
 426                 bytes_pp = 2;
 427                 break;
 428         case 8:
 429                 bytes_pp = 1;
 430                 break;
 431         default:
 432                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 433                 return -EINVAL;
 434         }
 435
 436         plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 437
 438         return 0;
 439 }
 440
 441 static int mxs_video_remove(struct udevice *dev)
 442 {
 443         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 444
 445         mxs_remove_common(plat->base);
 446
 447         return 0;
 448 }
 449
 450 static const struct udevice_id mxs_video_ids[] = {
 451         { .compatible = "fsl,imx23-lcdif" },
 452         { .compatible = "fsl,imx28-lcdif" },
 453         { .compatible = "fsl,imx7ulp-lcdif" },
 454         { .compatible = "fsl,imxrt-lcdif" },
 455         { /* sentinel */ }
 456 };
 457
 458 U_BOOT_DRIVER(mxs_video) = {
 459         .name   = "mxs_video",
 460         .id     = UCLASS_VIDEO,
 461         .of_match = mxs_video_ids,
 462         .bind   = mxs_video_bind,
 463         .probe  = mxs_video_probe,
 464         .remove = mxs_video_remove,
 465         .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 466 };
 467 #endif /* ifndef CONFIG_DM_VIDEO */